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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	bin.meng@windriver.com, richard.henderson@linaro.org,
	palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN
Date: Thu, 25 Nov 2021 15:39:32 +0800	[thread overview]
Message-ID: <20211125073951.57678-4-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com>

When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..a6a73ced9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        dest = (int32_t)dest;
+    }
+    tcg_gen_movi_tl(cpu_pc, dest);
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc(ctx, ctx->base.pc_next);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc(ctx, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
         tcg_gen_goto_tb(n);
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc(ctx, dest);
         tcg_gen_lookup_and_goto_ptr();
     }
 }
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com,
	palmer@dabbelt.com, bin.meng@windriver.com,
	LIU Zhiwei <zhiwei_liu@c-sky.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN
Date: Thu, 25 Nov 2021 15:39:32 +0800	[thread overview]
Message-ID: <20211125073951.57678-4-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211125073951.57678-1-zhiwei_liu@c-sky.com>

When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..a6a73ced9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        dest = (int32_t)dest;
+    }
+    tcg_gen_movi_tl(cpu_pc, dest);
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc(ctx, ctx->base.pc_next);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc(ctx, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
         tcg_gen_goto_tb(n);
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc(ctx, dest);
         tcg_gen_lookup_and_goto_ptr();
     }
 }
-- 
2.25.1



  parent reply	other threads:[~2021-11-25  7:56 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-25  7:39 [PATCH v5 00/22] Support UXL filed in xstatus LIU Zhiwei
2021-11-25  7:39 ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-26 11:19   ` Richard Henderson
2021-11-26 11:19     ` Richard Henderson
2021-11-25  7:39 ` [PATCH v5 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` LIU Zhiwei [this message]
2021-11-25  7:39   ` [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 04/22] target/riscv: Create xl field in env LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-26 11:25   ` Richard Henderson
2021-11-26 11:25     ` Richard Henderson
2021-11-25  7:39 ` [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 08/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 10/22] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-26 11:31   ` Richard Henderson
2021-11-26 11:31     ` Richard Henderson
2021-11-25  7:39 ` [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 12/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 14/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 19/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 20/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-26 11:33   ` Richard Henderson
2021-11-26 11:33     ` Richard Henderson
2021-11-25  7:39 ` [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei
2021-11-25  7:39 ` [PATCH v5 22/22] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-25  7:39   ` LIU Zhiwei

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