From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions Date: Mon, 29 Nov 2021 11:02:51 +0800 [thread overview] Message-ID: <20211129030340.429689-32-frank.chang@sifive.com> (raw) In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++- target/riscv/vector_helper.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4df2aa9cddc..d139c0aade7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3645bb96356..9206e6f06c8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2731,7 +2731,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd != a->rs2)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f97783acf05..b0dc971a860 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4260,7 +4260,6 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t vlmax = env_archcpu(env)->cfg.vlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; @@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, i, 0); - } } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions Date: Mon, 29 Nov 2021 11:02:51 +0800 [thread overview] Message-ID: <20211129030340.429689-32-frank.chang@sifive.com> (raw) In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++- target/riscv/vector_helper.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4df2aa9cddc..d139c0aade7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3645bb96356..9206e6f06c8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2731,7 +2731,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd != a->rs2)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f97783acf05..b0dc971a860 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4260,7 +4260,6 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t vlmax = env_archcpu(env)->cfg.vlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; @@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, i, 0); - } } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, -- 2.25.1
next prev parent reply other threads:[~2021-11-29 3:26 UTC|newest] Thread overview: 168+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-29 3:02 [PATCH v10 00/77] support vector extension v1.0 frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:16 ` Alistair Francis 2021-11-29 3:16 ` Alistair Francis 2021-11-29 3:02 ` [PATCH v10 05/77] target/riscv: rvv-1.0: add sstatus VS field frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 07/77] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 09/77] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 14/77] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 16/77] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 18/77] target/riscv: rvv-1.0: remove amo operations instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 19/77] target/riscv: rvv-1.0: configure instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 20/77] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 21/77] target/riscv: rvv-1.0: index " frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 24/77] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 27/77] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 28/77] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 29/77] target/riscv: rvv-1.0: count population in mask instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` frank.chang [this message] 2021-11-29 3:02 ` [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-11-29 3:02 ` [PATCH v10 32/77] target/riscv: rvv-1.0: iota instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 35/77] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 36/77] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:02 ` [PATCH v10 39/77] target/riscv: rvv-1.0: whole register " frank.chang 2021-11-29 3:02 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 40/77] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 47/77] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 48/77] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 49/77] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 50/77] target/riscv: rvv-1.0: slide instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 51/77] target/riscv: rvv-1.0: floating-point " frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 53/77] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 58/77] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 59/77] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 60/77] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 63/77] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 66/77] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-11-29 3:03 ` frank.chang 2021-12-08 3:32 ` Alistair Francis 2021-12-08 3:32 ` Alistair Francis 2021-11-29 3:03 ` [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-11-29 3:03 ` frank.chang 2021-12-08 3:38 ` Alistair Francis 2021-12-08 3:38 ` Alistair Francis 2021-11-29 3:03 ` [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang 2021-11-29 3:03 ` frank.chang 2021-11-29 3:03 ` [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions frank.chang 2021-11-29 3:03 ` frank.chang 2021-12-08 3:44 ` Alistair Francis 2021-12-08 3:44 ` Alistair Francis 2021-12-08 6:39 ` [PATCH v10 00/77] support vector extension v1.0 Alistair Francis 2021-12-08 6:39 ` Alistair Francis 2021-12-10 7:35 ` Frank Chang 2021-12-10 7:35 ` Frank Chang
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