From: jason-jh.lin <jason-jh.lin@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Alexandre Torgue <alexandre.torgue@foss.st.com>, <hsinyi@chromium.org>, <fshao@chromium.org>, <moudy.ho@mediatek.com>, <roy-cw.yeh@mediatek.com>, <jason-jh.lin@mediatek.com>, Fabien Parent <fparent@baylibre.com>, Yongqiang Niu <yongqiang.niu@mediatek.com>, <nancy.lin@mediatek.com>, <singo.chang@mediatek.com>, <devicetree@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v13 13/15] drm/mediatek: add DSC support for mediatek-drm Date: Tue, 30 Nov 2021 02:44:37 +0800 [thread overview] Message-ID: <20211129184439.16892-14-jason-jh.lin@mediatek.com> (raw) In-Reply-To: <20211129184439.16892-1-jason-jh.lin@mediatek.com> DSC is designed for real-time systems with real-time compression, transmission, decompression and display. The DSC standard is a specification of the algorithms used for compressing and decompressing image display streams, including the specification of the syntax and semantics of the compressed video bit stream. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> --- rebase on series [1] [1] drm/mediatek: add support for mediatek SOC MT8192 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489 --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b4b682bc1991..90b289b5f9a4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -40,6 +40,12 @@ #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) +#define DISP_REG_DSC_CON 0x0000 +#define DSC_EN BIT(0) +#define DSC_DUAL_INOUT BIT(2) +#define DSC_BYPASS BIT(4) +#define DSC_UFOE_SEL BIT(16) + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc, DISP_DITHERING, cmdq_pkt); } +static void mtk_dsc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + /* dsc bypass mode */ + mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_BYPASS); + mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_UFOE_SEL); + mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_DUAL_INOUT); +} + +static void mtk_dsc_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + /* write with mask to reserve the value set in mtk_dsc_config */ + mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); +} + +static void mtk_dsc_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON); +} + static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = { .stop = mtk_dpi_stop, }; +static const struct mtk_ddp_comp_funcs ddp_dsc = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_dsc_config, + .start = mtk_dsc_start, + .stop = mtk_dsc_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_dsi = { .start = mtk_dsi_ddp_start, .stop = mtk_dsi_ddp_stop, @@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_CCORR] = "ccorr", [MTK_DISP_COLOR] = "color", [MTK_DISP_DITHER] = "dither", + [MTK_DISP_DSC] = "dsc", [MTK_DISP_GAMMA] = "gamma", [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", @@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 4c6a98662305..5e6ff12f16ad 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type { MTK_DISP_CCORR, MTK_DISP_COLOR, MTK_DISP_DITHER, + MTK_DISP_DSC, MTK_DISP_GAMMA, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: jason-jh.lin <jason-jh.lin@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Alexandre Torgue <alexandre.torgue@foss.st.com>, <hsinyi@chromium.org>, <fshao@chromium.org>, <moudy.ho@mediatek.com>, <roy-cw.yeh@mediatek.com>, <jason-jh.lin@mediatek.com>, Fabien Parent <fparent@baylibre.com>, Yongqiang Niu <yongqiang.niu@mediatek.com>, <nancy.lin@mediatek.com>, <singo.chang@mediatek.com>, <devicetree@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v13 13/15] drm/mediatek: add DSC support for mediatek-drm Date: Tue, 30 Nov 2021 02:44:37 +0800 [thread overview] Message-ID: <20211129184439.16892-14-jason-jh.lin@mediatek.com> (raw) In-Reply-To: <20211129184439.16892-1-jason-jh.lin@mediatek.com> DSC is designed for real-time systems with real-time compression, transmission, decompression and display. The DSC standard is a specification of the algorithms used for compressing and decompressing image display streams, including the specification of the syntax and semantics of the compressed video bit stream. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> --- rebase on series [1] [1] drm/mediatek: add support for mediatek SOC MT8192 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489 --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b4b682bc1991..90b289b5f9a4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -40,6 +40,12 @@ #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) +#define DISP_REG_DSC_CON 0x0000 +#define DSC_EN BIT(0) +#define DSC_DUAL_INOUT BIT(2) +#define DSC_BYPASS BIT(4) +#define DSC_UFOE_SEL BIT(16) + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc, DISP_DITHERING, cmdq_pkt); } +static void mtk_dsc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + /* dsc bypass mode */ + mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_BYPASS); + mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_UFOE_SEL); + mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_DUAL_INOUT); +} + +static void mtk_dsc_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + /* write with mask to reserve the value set in mtk_dsc_config */ + mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); +} + +static void mtk_dsc_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON); +} + static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = { .stop = mtk_dpi_stop, }; +static const struct mtk_ddp_comp_funcs ddp_dsc = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_dsc_config, + .start = mtk_dsc_start, + .stop = mtk_dsc_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_dsi = { .start = mtk_dsi_ddp_start, .stop = mtk_dsi_ddp_stop, @@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_CCORR] = "ccorr", [MTK_DISP_COLOR] = "color", [MTK_DISP_DITHER] = "dither", + [MTK_DISP_DSC] = "dsc", [MTK_DISP_GAMMA] = "gamma", [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", @@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 4c6a98662305..5e6ff12f16ad 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type { MTK_DISP_CCORR, MTK_DISP_COLOR, MTK_DISP_DITHER, + MTK_DISP_DSC, MTK_DISP_GAMMA, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-11-29 18:59 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-29 18:44 [PATCH v13 00/15] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 01/15] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 02/15] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 03/15] dt-bindings: display: mediatek: disp: split each block to individual yaml jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 04/15] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 05/15] dt-bindings: display: mediatek: merge: add additional prop for mt8195 jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 06/15] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0 jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 07/15] dt-bindings: arm: mediatek: move common module from display folder jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 08/15] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 09/15] soc: mediatek: add mtk-mutex " jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 10/15] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-12-03 0:06 ` Chun-Kuang Hu 2021-12-03 0:06 ` Chun-Kuang Hu 2021-12-03 0:06 ` Chun-Kuang Hu 2021-11-29 18:44 ` [PATCH v13 11/15] drm/mediatek: rename the define of register offset jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-12-03 0:07 ` Chun-Kuang Hu 2021-12-03 0:07 ` Chun-Kuang Hu 2021-11-29 18:44 ` [PATCH v13 12/15] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-12-03 0:07 ` Chun-Kuang Hu 2021-12-03 0:07 ` Chun-Kuang Hu 2021-11-29 18:44 ` jason-jh.lin [this message] 2021-11-29 18:44 ` [PATCH v13 13/15] drm/mediatek: add DSC support " jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 14/15] drm/mediatek: add MERGE " jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin 2021-11-29 18:44 ` [PATCH v13 15/15] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin 2021-11-29 18:44 ` jason-jh.lin
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211129184439.16892-14-jason-jh.lin@mediatek.com \ --to=jason-jh.lin@mediatek.com \ --cc=airlied@linux.ie \ --cc=alexandre.torgue@foss.st.com \ --cc=angelogioacchino.delregno@collabora.com \ --cc=chunkuang.hu@kernel.org \ --cc=daniel@ffwll.ch \ --cc=devicetree@vger.kernel.org \ --cc=enric.balletbo@collabora.com \ --cc=fparent@baylibre.com \ --cc=fshao@chromium.org \ --cc=hsinyi@chromium.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mediatek@lists.infradead.org \ --cc=linux-stm32@st-md-mailman.stormreply.com \ --cc=matthias.bgg@gmail.com \ --cc=mcoquelin.stm32@gmail.com \ --cc=moudy.ho@mediatek.com \ --cc=nancy.lin@mediatek.com \ --cc=p.zabel@pengutronix.de \ --cc=robh+dt@kernel.org \ --cc=roy-cw.yeh@mediatek.com \ --cc=singo.chang@mediatek.com \ --cc=yongqiang.niu@mediatek.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.