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From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: pali@kernel.org, linux-pci@vger.kernel.org,
	"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v4 04/11] PCI: aardvark: Clear all MSIs at setup
Date: Tue, 30 Nov 2021 18:29:06 +0100	[thread overview]
Message-ID: <20211130172913.9727-5-kabel@kernel.org> (raw)
In-Reply-To: <20211130172913.9727-1-kabel@kernel.org>

From: Pali Rohár <pali@kernel.org>

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 25af189a1052..71ce9f02d596 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -116,6 +116,7 @@
 #define PCIE_MSI_ADDR_HIGH_REG			(CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG			(CONTROL_BASE_ADDR + 0x58)
 #define PCIE_MSI_MASK_REG			(CONTROL_BASE_ADDR + 0x5C)
+#define     PCIE_MSI_ALL_MASK			GENMASK(31, 0)
 #define PCIE_MSI_PAYLOAD_REG			(CONTROL_BASE_ADDR + 0x9C)
 #define     PCIE_MSI_DATA_MASK			GENMASK(15, 0)
 
@@ -571,6 +572,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 
 	/* Clear all interrupts */
+	advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
 	advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
 	advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
@@ -583,7 +585,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
 
 	/* Unmask all MSIs */
-	advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
+	advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
 
 	/* Enable summary interrupt for GIC SPI source */
 	reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
@@ -1399,7 +1401,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 
 	msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
 	msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
-	msi_status = msi_val & ~msi_mask;
+	msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
 
 	for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
 		if (!(BIT(msi_idx) & msi_status))
-- 
2.32.0


  parent reply	other threads:[~2021-11-30 17:29 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-30 17:29 [PATCH v4 00/11] PCI: aardvark controller fixes BATCH 3 Marek Behún
2021-11-30 17:29 ` [PATCH v4 01/11] PCI: pci-bridge-emul: Add description for class_revision field Marek Behún
2021-12-03 16:36   ` Bjorn Helgaas
2021-12-03 18:52     ` Marek Behún
2021-11-30 17:29 ` [PATCH v4 02/11] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Marek Behún
2021-12-03 16:45   ` Bjorn Helgaas
2021-11-30 17:29 ` [PATCH v4 03/11] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Marek Behún
2021-11-30 17:29 ` Marek Behún [this message]
2021-11-30 17:29 ` [PATCH v4 05/11] PCI: aardvark: Comment actions in driver remove method Marek Behún
2021-11-30 17:29 ` [PATCH v4 06/11] PCI: aardvark: Disable bus mastering when unbinding driver Marek Behún
2021-11-30 17:29 ` [PATCH v4 07/11] PCI: aardvark: Mask all interrupts " Marek Behún
2021-11-30 17:29 ` [PATCH v4 08/11] PCI: aardvark: Fix memory leak in driver unbind Marek Behún
2021-11-30 17:29 ` [PATCH v4 09/11] PCI: aardvark: Assert PERST# when unbinding driver Marek Behún
2021-11-30 17:29 ` [PATCH v4 10/11] PCI: aardvark: Disable link training " Marek Behún
2021-11-30 17:29 ` [PATCH v4 11/11] PCI: aardvark: Disable common PHY " Marek Behún
2021-12-02 10:01 ` [PATCH v4 00/11] PCI: aardvark controller fixes BATCH 3 Lorenzo Pieralisi

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