From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, "Thomas Hellström" <thomas.hellstrom@linux.intel.com> Subject: [PATCH v3 5/8] drm/i915/gtt: allow overriding the pt alignment Date: Mon, 6 Dec 2021 13:31:37 +0000 [thread overview] Message-ID: <20211206133140.3166205-6-matthew.auld@intel.com> (raw) In-Reply-To: <20211206133140.3166205-1-matthew.auld@intel.com> On some platforms we have alignment restrictions when accessing LMEM from the GTT. In the next patch few patches we need to be able to modify the page-tables directly via the GTT itself. Suggested-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +++++++++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 ++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index cbc0b5266cb4..a00d278d8175 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -196,6 +196,14 @@ void *__px_vaddr(struct drm_i915_gem_object *p); struct i915_vm_pt_stash { /* preallocated chains of page tables/directories */ struct i915_page_table *pt[2]; + /* + * Optionally override the alignment/size of the physical page that + * contains each PT. If not set defaults back to the usual + * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging + * structures. MUST be a power-of-two. ONLY applicable on discrete + * platforms. + */ + int pt_sz; }; struct i915_vma_ops { @@ -583,7 +591,7 @@ void free_scratch(struct i915_address_space *vm); struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); -struct i915_page_table *alloc_pt(struct i915_address_space *vm); +struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); struct i915_page_directory *alloc_pd(struct i915_address_space *vm); struct i915_page_directory *__alloc_pd(int npde); diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index b8238f5bc8b1..3c90aea25072 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -12,7 +12,7 @@ #include "gen6_ppgtt.h" #include "gen8_ppgtt.h" -struct i915_page_table *alloc_pt(struct i915_address_space *vm) +struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz) { struct i915_page_table *pt; @@ -20,7 +20,7 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm) if (unlikely(!pt)) return ERR_PTR(-ENOMEM); - pt->base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + pt->base = vm->alloc_pt_dma(vm, sz); if (IS_ERR(pt->base)) { kfree(pt); return ERR_PTR(-ENOMEM); @@ -219,17 +219,25 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm, u64 size) { unsigned long count; - int shift, n; + int shift, n, pt_sz; shift = vm->pd_shift; if (!shift) return 0; + pt_sz = stash->pt_sz; + if (!pt_sz) + pt_sz = I915_GTT_PAGE_SIZE_4K; + else + GEM_BUG_ON(!IS_DGFX(vm->i915)); + + GEM_BUG_ON(!is_power_of_2(pt_sz)); + count = pd_count(size, shift); while (count--) { struct i915_page_table *pt; - pt = alloc_pt(vm); + pt = alloc_pt(vm, pt_sz); if (IS_ERR(pt)) { i915_vm_free_pt_stash(vm, stash); return PTR_ERR(pt); -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, "Thomas Hellström" <thomas.hellstrom@linux.intel.com> Subject: [Intel-gfx] [PATCH v3 5/8] drm/i915/gtt: allow overriding the pt alignment Date: Mon, 6 Dec 2021 13:31:37 +0000 [thread overview] Message-ID: <20211206133140.3166205-6-matthew.auld@intel.com> (raw) In-Reply-To: <20211206133140.3166205-1-matthew.auld@intel.com> On some platforms we have alignment restrictions when accessing LMEM from the GTT. In the next patch few patches we need to be able to modify the page-tables directly via the GTT itself. Suggested-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +++++++++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 ++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index cbc0b5266cb4..a00d278d8175 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -196,6 +196,14 @@ void *__px_vaddr(struct drm_i915_gem_object *p); struct i915_vm_pt_stash { /* preallocated chains of page tables/directories */ struct i915_page_table *pt[2]; + /* + * Optionally override the alignment/size of the physical page that + * contains each PT. If not set defaults back to the usual + * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging + * structures. MUST be a power-of-two. ONLY applicable on discrete + * platforms. + */ + int pt_sz; }; struct i915_vma_ops { @@ -583,7 +591,7 @@ void free_scratch(struct i915_address_space *vm); struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); -struct i915_page_table *alloc_pt(struct i915_address_space *vm); +struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); struct i915_page_directory *alloc_pd(struct i915_address_space *vm); struct i915_page_directory *__alloc_pd(int npde); diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index b8238f5bc8b1..3c90aea25072 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -12,7 +12,7 @@ #include "gen6_ppgtt.h" #include "gen8_ppgtt.h" -struct i915_page_table *alloc_pt(struct i915_address_space *vm) +struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz) { struct i915_page_table *pt; @@ -20,7 +20,7 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm) if (unlikely(!pt)) return ERR_PTR(-ENOMEM); - pt->base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + pt->base = vm->alloc_pt_dma(vm, sz); if (IS_ERR(pt->base)) { kfree(pt); return ERR_PTR(-ENOMEM); @@ -219,17 +219,25 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm, u64 size) { unsigned long count; - int shift, n; + int shift, n, pt_sz; shift = vm->pd_shift; if (!shift) return 0; + pt_sz = stash->pt_sz; + if (!pt_sz) + pt_sz = I915_GTT_PAGE_SIZE_4K; + else + GEM_BUG_ON(!IS_DGFX(vm->i915)); + + GEM_BUG_ON(!is_power_of_2(pt_sz)); + count = pd_count(size, shift); while (count--) { struct i915_page_table *pt; - pt = alloc_pt(vm); + pt = alloc_pt(vm, pt_sz); if (IS_ERR(pt)) { i915_vm_free_pt_stash(vm, stash); return PTR_ERR(pt); -- 2.31.1
next prev parent reply other threads:[~2021-12-06 13:32 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-06 13:31 [PATCH v3 0/8] DG2 accelerated migration/clearing support Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 1/8] drm/i915/migrate: don't check the scratch page Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 2/8] drm/i915/migrate: fix offset calculation Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 3/8] drm/i915/migrate: fix length calculation Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 4/8] drm/i915/selftests: handle object rounding Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` Matthew Auld [this message] 2021-12-06 13:31 ` [Intel-gfx] [PATCH v3 5/8] drm/i915/gtt: allow overriding the pt alignment Matthew Auld 2021-12-13 15:32 ` Ramalingam C 2021-12-13 15:32 ` [Intel-gfx] " Ramalingam C 2021-12-06 13:31 ` [PATCH v3 6/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 13:31 ` [PATCH v3 7/8] drm/i915/migrate: add acceleration support for DG2 Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-14 10:56 ` Ramalingam C 2021-12-14 10:56 ` [Intel-gfx] " Ramalingam C 2021-12-14 12:32 ` Matthew Auld 2021-12-14 12:32 ` [Intel-gfx] " Matthew Auld 2021-12-16 15:01 ` Ramalingam C 2021-12-16 15:01 ` [Intel-gfx] " Ramalingam C 2021-12-06 13:31 ` [PATCH v3 8/8] drm/i915/migrate: turn on acceleration " Matthew Auld 2021-12-06 13:31 ` [Intel-gfx] " Matthew Auld 2021-12-06 14:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 accelerated migration/clearing support (rev2) Patchwork 2021-12-06 14:49 ` [PATCH v3 0/8] DG2 accelerated migration/clearing support Daniel Stone 2021-12-06 14:49 ` [Intel-gfx] " Daniel Stone 2021-12-06 15:13 ` Matthew Auld 2021-12-06 15:13 ` [Intel-gfx] " Matthew Auld
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211206133140.3166205-6-matthew.auld@intel.com \ --to=matthew.auld@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=thomas.hellstrom@linux.intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.