From: Michael Ellerman <mpe@ellerman.id.au>
To: <linuxppc-dev@lists.ozlabs.org>
Cc: sachinp@linux.ibm.com, npiggin@gmail.com
Subject: [PATCH 1/3] powerpc/64s: Mask NIP before checking against SRR0
Date: Wed, 22 Dec 2021 00:50:59 +1100 [thread overview]
Message-ID: <20211221135101.2085547-1-mpe@ellerman.id.au> (raw)
When CONFIG_PPC_RFI_SRR_DEBUG=y we check that NIP and SRR0 match when
returning from interrupts. This can trigger falsely if NIP has either of
its two low bits set via sigreturn or ptrace, while SRR0 has its low two
bits masked in hardware.
As a quick fix make sure to mask the low bits before doing the check.
Fixes: 59dc5bfca0cb ("powerpc/64s: avoid reloading (H)SRR registers if they are still valid")
Reported-by: Sachin Sant <sachinp@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/kernel/interrupt_64.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/interrupt_64.S
index 2ad223597ca2..4fd65d39d5d3 100644
--- a/arch/powerpc/kernel/interrupt_64.S
+++ b/arch/powerpc/kernel/interrupt_64.S
@@ -30,6 +30,7 @@
.ifc \srr,srr
mfspr r11,SPRN_SRR0
ld r12,_NIP(r1)
+ clrrdi r12,r12,2
100: tdne r11,r12
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
mfspr r11,SPRN_SRR1
@@ -39,6 +40,7 @@
.else
mfspr r11,SPRN_HSRR0
ld r12,_NIP(r1)
+ clrrdi r12,r12,2
100: tdne r11,r12
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
mfspr r11,SPRN_HSRR1
--
2.31.1
next reply other threads:[~2021-12-21 13:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 13:50 Michael Ellerman [this message]
2021-12-21 13:51 ` [PATCH 2/3] powerpc/64s: Use EMIT_WARN_ENTRY for SRR debug warnings Michael Ellerman
2021-12-21 13:51 ` [PATCH 3/3] selftests/powerpc: Add a test of sigreturning to an unaligned address Michael Ellerman
2021-12-22 10:25 ` [PATCH 1/3] powerpc/64s: Mask NIP before checking against SRR0 Sachin Sant
2021-12-26 21:52 ` Michael Ellerman
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