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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>
Cc: Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>,
	Julien Su <juliensu@mxic.com.tw>,
	Jaime Liao <jaimeliao@mxic.com.tw>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Xiangsheng Hou <xiangsheng.hou@mediatek.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v8 07/14] spi: spi-mem: Add an ecc parameter to the spi_mem_op structure
Date: Tue, 21 Dec 2021 18:48:37 +0100	[thread overview]
Message-ID: <20211221174844.56385-8-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20211221174844.56385-1-miquel.raynal@bootlin.com>

Soon the SPI-NAND core will need a way to request a SPI controller to
enable ECC support for a given operation. This is because of the
pipelined integration of certain ECC engines, which are directly managed
by the SPI controller itself.

Introduce a spi_mem_op additional field for this purpose: ecc.

So far this field is left unset and checked to be false by all
the SPI controller drivers in their ->supports_op() hook, as they all
call spi_mem_default_supports_op().

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/spi/spi-mem.c       | 5 +++++
 include/linux/spi/spi-mem.h | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index ccc606f741ae..3ff39771cdd4 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -190,6 +190,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
 			return false;
 	}
 
+	if (op->data.ecc) {
+		if (!spi_mem_controller_is_capable(ctlr, ecc))
+			return false;
+	}
+
 	return spi_mem_check_buswidth(mem, op);
 }
 EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index d7787c8f3746..a8e8287fdbd0 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  * @data.buswidth: number of IO lanes used to send/receive the data
  * @data.dtr: whether the data should be sent in DTR mode or not
+ * @data.ecc: whether error correction is required or not
  * @data.dir: direction of the transfer
  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  *		 operation does not involve transferring data
@@ -119,6 +120,7 @@ struct spi_mem_op {
 	struct {
 		u8 buswidth;
 		u8 dtr : 1;
+		u8 ecc : 1;
 		enum spi_mem_data_dir dir;
 		unsigned int nbytes;
 		union {
@@ -126,6 +128,7 @@ struct spi_mem_op {
 			const void *out;
 		} buf;
 	} data;
+
 };
 
 #define SPI_MEM_OP(__cmd, __addr, __dummy, __data)		\
@@ -223,9 +226,11 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
 /**
  * struct spi_controller_mem_caps - SPI memory controller capabilities
  * @dtr: Supports DTR operations
+ * @ecc: Supports operations with error correction
  */
 struct spi_controller_mem_caps {
 	bool dtr;
+	bool ecc;
 };
 
 #define spi_mem_controller_is_capable(ctlr, cap)		\
-- 
2.27.0


WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>
Cc: Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>,
	Julien Su <juliensu@mxic.com.tw>,
	Jaime Liao <jaimeliao@mxic.com.tw>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Xiangsheng Hou <xiangsheng.hou@mediatek.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v8 07/14] spi: spi-mem: Add an ecc parameter to the spi_mem_op structure
Date: Tue, 21 Dec 2021 18:48:37 +0100	[thread overview]
Message-ID: <20211221174844.56385-8-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20211221174844.56385-1-miquel.raynal@bootlin.com>

Soon the SPI-NAND core will need a way to request a SPI controller to
enable ECC support for a given operation. This is because of the
pipelined integration of certain ECC engines, which are directly managed
by the SPI controller itself.

Introduce a spi_mem_op additional field for this purpose: ecc.

So far this field is left unset and checked to be false by all
the SPI controller drivers in their ->supports_op() hook, as they all
call spi_mem_default_supports_op().

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/spi/spi-mem.c       | 5 +++++
 include/linux/spi/spi-mem.h | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index ccc606f741ae..3ff39771cdd4 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -190,6 +190,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
 			return false;
 	}
 
+	if (op->data.ecc) {
+		if (!spi_mem_controller_is_capable(ctlr, ecc))
+			return false;
+	}
+
 	return spi_mem_check_buswidth(mem, op);
 }
 EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index d7787c8f3746..a8e8287fdbd0 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  * @data.buswidth: number of IO lanes used to send/receive the data
  * @data.dtr: whether the data should be sent in DTR mode or not
+ * @data.ecc: whether error correction is required or not
  * @data.dir: direction of the transfer
  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  *		 operation does not involve transferring data
@@ -119,6 +120,7 @@ struct spi_mem_op {
 	struct {
 		u8 buswidth;
 		u8 dtr : 1;
+		u8 ecc : 1;
 		enum spi_mem_data_dir dir;
 		unsigned int nbytes;
 		union {
@@ -126,6 +128,7 @@ struct spi_mem_op {
 			const void *out;
 		} buf;
 	} data;
+
 };
 
 #define SPI_MEM_OP(__cmd, __addr, __dummy, __data)		\
@@ -223,9 +226,11 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
 /**
  * struct spi_controller_mem_caps - SPI memory controller capabilities
  * @dtr: Supports DTR operations
+ * @ecc: Supports operations with error correction
  */
 struct spi_controller_mem_caps {
 	bool dtr;
+	bool ecc;
 };
 
 #define spi_mem_controller_is_capable(ctlr, cap)		\
-- 
2.27.0


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  parent reply	other threads:[~2021-12-21 17:49 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-21 17:48 [PATCH v8 00/14] External ECC engines & Macronix support Miquel Raynal
2021-12-21 17:48 ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 01/14] spi: spi-mem: reject partial cycle transfers in Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 18:41   ` Pratyush Yadav
2021-12-21 18:41     ` Pratyush Yadav
2021-12-22  8:12     ` Miquel Raynal
2021-12-22  8:12       ` Miquel Raynal
2021-12-22  8:31       ` Pratyush Yadav
2021-12-22  8:31         ` Pratyush Yadav
2021-12-22  8:33         ` Miquel Raynal
2021-12-22  8:33           ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 02/14] spi: spi-mem: Introduce a capability structure Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 03/14] spi: spi-mem: Check the controller extra capabilities Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 04/14] spi: cadence-quadspi: Provide a capability structure Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 18:42   ` Pratyush Yadav
2021-12-21 18:42     ` Pratyush Yadav
2021-12-21 17:48 ` [PATCH v8 05/14] spi: mxic: " Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 06/14] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` Miquel Raynal [this message]
2021-12-21 17:48   ` [PATCH v8 07/14] spi: spi-mem: Add an ecc parameter to the spi_mem_op structure Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 08/14] mtd: spinand: Delay a little bit the dirmap creation Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 09/14] mtd: spinand: Create direct mapping descriptors for ECC operations Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 10/14] spi: mxic: Fix the transmit path Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 11/14] spi: mxic: Create a helper to configure the controller before an operation Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 12/14] spi: mxic: Create a helper to ease the start of " Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 13/14] spi: mxic: Add support for direct mapping Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-21 17:48 ` [PATCH v8 14/14] spi: mxic: Add support for pipelined ECC operations Miquel Raynal
2021-12-21 17:48   ` Miquel Raynal
2021-12-30 15:54 ` [PATCH v8 00/14] External ECC engines & Macronix support Miquel Raynal
2021-12-30 15:54   ` Miquel Raynal

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