From: Atish Patra <atishp@atishpatra.org> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v2 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Date: Tue, 28 Dec 2021 14:30:53 -0800 [thread overview] Message-ID: <20211228223057.2772727-3-atishp@rivosinc.com> (raw) In-Reply-To: <20211228223057.2772727-1-atishp@rivosinc.com> The HSM extension information log also prints the SBI version v0.2. This is misleading as the underlying firmware SBI version may be different from v0.2. Remove the unncessary printing of SBI version. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/kernel/cpu_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index 1985884fe829..3f5a38b03044 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -38,7 +38,7 @@ void __init cpu_set_ops(int cpuid) #if IS_ENABLED(CONFIG_RISCV_SBI) if (sbi_probe_extension(SBI_EXT_HSM) > 0) { if (!cpuid) - pr_info("SBI v0.2 HSM extension detected\n"); + pr_info("SBI HSM extension detected\n"); cpu_ops[cpuid] = &cpu_ops_sbi; } else #endif -- 2.33.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@atishpatra.org> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v2 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Date: Tue, 28 Dec 2021 14:30:53 -0800 [thread overview] Message-ID: <20211228223057.2772727-3-atishp@rivosinc.com> (raw) In-Reply-To: <20211228223057.2772727-1-atishp@rivosinc.com> The HSM extension information log also prints the SBI version v0.2. This is misleading as the underlying firmware SBI version may be different from v0.2. Remove the unncessary printing of SBI version. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/kernel/cpu_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index 1985884fe829..3f5a38b03044 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -38,7 +38,7 @@ void __init cpu_set_ops(int cpuid) #if IS_ENABLED(CONFIG_RISCV_SBI) if (sbi_probe_extension(SBI_EXT_HSM) > 0) { if (!cpuid) - pr_info("SBI v0.2 HSM extension detected\n"); + pr_info("SBI HSM extension detected\n"); cpu_ops[cpuid] = &cpu_ops_sbi; } else #endif -- 2.33.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-28 22:31 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-28 22:30 [PATCH v2 0/6] Sparse HART id support Atish Patra 2021-12-28 22:30 ` Atish Patra 2021-12-28 22:30 ` [PATCH v2 1/6] RISC-V: Avoid using per cpu array for ordered booting Atish Patra 2021-12-28 22:30 ` Atish Patra 2022-01-07 15:13 ` Anup Patel 2022-01-07 15:13 ` Anup Patel 2021-12-28 22:30 ` Atish Patra [this message] 2021-12-28 22:30 ` [PATCH v2 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Atish Patra 2021-12-28 22:30 ` [PATCH v2 3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Atish Patra 2021-12-28 22:30 ` Atish Patra 2021-12-28 22:30 ` [PATCH v2 4/6] RISC-V: Move the entire hart selection via lottery to SMP Atish Patra 2022-01-07 15:14 ` Anup Patel 2021-12-28 22:30 ` [PATCH v2 5/6] RISC-V: Move spinwait booting method to its own config Atish Patra 2021-12-28 22:30 ` Atish Patra 2022-01-07 15:15 ` Anup Patel 2022-01-07 15:15 ` Anup Patel 2021-12-28 22:30 ` [PATCH v2 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Atish Patra 2021-12-28 22:30 ` Atish Patra 2022-01-07 15:22 ` Anup Patel 2022-01-07 15:22 ` Anup Patel
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211228223057.2772727-3-atishp@rivosinc.com \ --to=atishp@atishpatra.org \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=atishp@rivosinc.com \ --cc=damien.lemoal@wdc.com \ --cc=devicetree@vger.kernel.org \ --cc=jszhang@kernel.org \ --cc=krzysztof.kozlowski@canonical.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.