All of lore.kernel.org
 help / color / mirror / Atom feed
From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, danielhb413@gmail.com,
	qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au
Subject: [PATCH v2 5/7] target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian
Date: Wed,  5 Jan 2022 17:40:27 -0300	[thread overview]
Message-ID: <20220105204029.4058500-6-farosas@linux.ibm.com> (raw)
In-Reply-To: <20220105204029.4058500-1-farosas@linux.ibm.com>

Some CPUs set ILE via an MSR bit. We can make
ppc_interrupts_little_endian handle that case as well. Now we have a
centralized way of determining the endianness of interrupts.

This change has no functional impact.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/cpu.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a6fc857ad4..f99cd0ea92 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2733,7 +2733,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
 {
     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
     CPUPPCState *env = &cpu->env;
-    bool ile = false;
+    bool ile;
 
     if (hv && env->has_hv_mode) {
         if (is_isa300(pcc)) {
@@ -2744,6 +2744,8 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
 
     } else if (pcc->lpcr_mask & LPCR_ILE) {
         ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
+    } else {
+        ile = !!(msr_ile);
     }
 
     return ile;
-- 
2.33.1



  parent reply	other threads:[~2022-01-05 20:52 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05 20:40 [PATCH v2 0/7] target/ppc: powerpc_excp improvements (2/n) Fabiano Rosas
2022-01-05 20:40 ` [PATCH v2 1/7] target/ppc: powerpc_excp: Extract software TLB logging into a function Fabiano Rosas
2022-01-06  3:55   ` David Gibson
2022-01-07  1:37   ` Richard Henderson
2022-01-05 20:40 ` [PATCH v2 2/7] target/ppc: powerpc_excp: Keep 60x soft MMU logs active Fabiano Rosas
2022-01-06  5:26   ` David Gibson
2022-01-07  1:40   ` Richard Henderson
2022-01-05 20:40 ` [PATCH v2 3/7] target/ppc: powerpc_excp: Group unimplemented exceptions Fabiano Rosas
2022-01-06  5:26   ` David Gibson
2022-01-07  3:07   ` Richard Henderson
2022-01-05 20:40 ` [PATCH v2 4/7] target/ppc: Add HV support to ppc_interrupts_little_endian Fabiano Rosas
2022-01-06  5:30   ` David Gibson
2022-01-06 13:05     ` Cédric Le Goater
2022-01-05 20:40 ` Fabiano Rosas [this message]
2022-01-06  5:30   ` [PATCH v2 5/7] target/ppc: Add MSR_ILE " David Gibson
2022-01-05 20:40 ` [PATCH v2 6/7] target/ppc: Use ppc_interrupts_little_endian in powerpc_excp Fabiano Rosas
2022-01-06  5:31   ` David Gibson
2022-01-05 20:40 ` [PATCH v2 7/7] target/ppc: Introduce a wrapper for powerpc_excp Fabiano Rosas
2022-01-06  5:31   ` David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220105204029.4058500-6-farosas@linux.ibm.com \
    --to=farosas@linux.ibm.com \
    --cc=clg@kaod.org \
    --cc=danielhb413@gmail.com \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.