From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
Date: Thu, 13 Jan 2022 19:40:04 +0800 [thread overview]
Message-ID: <20220113114004.286796-23-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220113114004.286796-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d944ee9caf..1037c6b15d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -580,7 +580,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
- if (xl != MXL_RV32) {
+ if (xl != MXL_RV32 || env->debugger) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
@@ -905,7 +905,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
/* TODO: Use SXL not MXL. */
@@ -917,7 +917,8 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, richard.henderson@linaro.org,
guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
Date: Thu, 13 Jan 2022 19:40:04 +0800 [thread overview]
Message-ID: <20220113114004.286796-23-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220113114004.286796-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d944ee9caf..1037c6b15d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -580,7 +580,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
- if (xl != MXL_RV32) {
+ if (xl != MXL_RV32 || env->debugger) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
@@ -905,7 +905,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
/* TODO: Use SXL not MXL. */
@@ -917,7 +917,8 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
--
2.25.1
next prev parent reply other threads:[~2022-01-13 12:25 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-13 11:39 [PATCH v6 00/22] Support UXL filed in xstatus LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-19 3:20 ` Alistair Francis
2022-01-19 3:20 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-19 3:21 ` Alistair Francis
2022-01-19 3:21 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 05/22] target/riscv: Create xl field in env LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-19 3:24 ` Alistair Francis
2022-01-19 3:24 ` Alistair Francis
2022-01-19 3:36 ` LIU Zhiwei
2022-01-19 3:36 ` LIU Zhiwei
2022-01-19 3:43 ` Alistair Francis
2022-01-19 3:43 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 11/22] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-13 11:39 ` LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-13 11:40 ` LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-13 11:40 ` LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-13 11:40 ` LIU Zhiwei
2022-01-19 3:30 ` Alistair Francis
2022-01-19 3:30 ` Alistair Francis
2022-01-13 11:40 ` [PATCH v6 21/22] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-13 11:40 ` LIU Zhiwei
2022-01-13 11:40 ` LIU Zhiwei [this message]
2022-01-13 11:40 ` [PATCH v6 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-19 3:34 ` Alistair Francis
2022-01-19 3:34 ` Alistair Francis
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