From: Alim Akhtar <alim.akhtar@samsung.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar <alim.akhtar@samsung.com>, linux-fsd@tesla.com Subject: [PATCH 02/23] dt-bindings: clock: Add bindings definitions for FSD CMU blocks Date: Thu, 13 Jan 2022 17:41:22 +0530 [thread overview] Message-ID: <20220113121143.22280-3-alim.akhtar@samsung.com> (raw) In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> Clock controller driver of FSD platform is designed to have separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU block. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> --- include/dt-bindings/clock/fsd-clk.h | 146 ++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 include/dt-bindings/clock/fsd-clk.h diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h new file mode 100644 index 000000000000..9b97417ea6a1 --- /dev/null +++ b/include/dt-bindings/clock/fsd-clk.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * The constants defined in this header are being used in dts + * and fsd platform driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_FSD_H +#define _DT_BINDINGS_CLOCK_FSD_H + +/* CMU */ +#define DOUT_CMU_PLL_SHARED0_DIV4 1 +#define DOUT_CMU_PERIC_SHARED1DIV36 2 +#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 +#define DOUT_CMU_PERIC_SHARED0DIV20 4 +#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 +#define DOUT_CMU_PLL_SHARED0_DIV6 6 +#define DOUT_CMU_FSYS0_SHARED1DIV4 7 +#define DOUT_CMU_FSYS0_SHARED0DIV4 8 +#define DOUT_CMU_FSYS1_SHARED0DIV8 9 +#define DOUT_CMU_FSYS1_SHARED0DIV4 10 +#define CMU_CPUCL_SWITCH_GATE 11 +#define DOUT_CMU_IMEM_TCUCLK 12 +#define DOUT_CMU_IMEM_ACLK 13 +#define DOUT_CMU_IMEM_DMACLK 14 +#define GAT_CMU_FSYS0_SHARED0DIV4 15 +#define CMU_NR_CLK 16 + +/* PERIC */ +#define PERIC_SCLK_UART0 1 +#define PERIC_PCLK_UART0 2 +#define PERIC_SCLK_UART1 3 +#define PERIC_PCLK_UART1 4 +#define PERIC_DMA0_IPCLKPORT_ACLK 5 +#define PERIC_DMA1_IPCLKPORT_ACLK 6 +#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 +#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 +#define PERIC_PCLK_SPI0 9 +#define PERIC_SCLK_SPI0 10 +#define PERIC_PCLK_SPI1 11 +#define PERIC_SCLK_SPI1 12 +#define PERIC_PCLK_SPI2 13 +#define PERIC_SCLK_SPI2 14 +#define PERIC_PCLK_TDM0 15 +#define PERIC_PCLK_HSI2C0 16 +#define PERIC_PCLK_HSI2C1 17 +#define PERIC_PCLK_HSI2C2 18 +#define PERIC_PCLK_HSI2C3 19 +#define PERIC_PCLK_HSI2C4 20 +#define PERIC_PCLK_HSI2C5 21 +#define PERIC_PCLK_HSI2C6 22 +#define PERIC_PCLK_HSI2C7 23 +#define PERIC_MCAN0_IPCLKPORT_CCLK 24 +#define PERIC_MCAN0_IPCLKPORT_PCLK 25 +#define PERIC_MCAN1_IPCLKPORT_CCLK 26 +#define PERIC_MCAN1_IPCLKPORT_PCLK 27 +#define PERIC_MCAN2_IPCLKPORT_CCLK 28 +#define PERIC_MCAN2_IPCLKPORT_PCLK 29 +#define PERIC_MCAN3_IPCLKPORT_CCLK 30 +#define PERIC_MCAN3_IPCLKPORT_PCLK 31 +#define PERIC_PCLK_ADCIF 32 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 +#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 +#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 +#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 +#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 +#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 +#define PERIC_HCLK_TDM0 40 +#define PERIC_PCLK_TDM1 41 +#define PERIC_HCLK_TDM1 42 +#define PERIC_EQOS_PHYRXCLK_MUX 43 +#define PERIC_EQOS_PHYRXCLK 44 +#define PERIC_DOUT_RGMII_CLK 45 +#define PERIC_NR_CLK 46 + +/* FSYS0 */ +#define UFS0_MPHY_REFCLK_IXTAL24 1 +#define UFS0_MPHY_REFCLK_IXTAL26 2 +#define UFS1_MPHY_REFCLK_IXTAL24 3 +#define UFS1_MPHY_REFCLK_IXTAL26 4 +#define UFS0_TOP0_HCLK_BUS 5 +#define UFS0_TOP0_ACLK 6 +#define UFS0_TOP0_CLK_UNIPRO 7 +#define UFS0_TOP0_FMP_CLK 8 +#define UFS1_TOP1_HCLK_BUS 9 +#define UFS1_TOP1_ACLK 10 +#define UFS1_TOP1_CLK_UNIPRO 11 +#define UFS1_TOP1_FMP_CLK 12 +#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 +#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 +#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 +#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 +#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 +#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 +#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 +#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 +#define FSYS0_NR_CLK 23 + +/* FSYS1 */ +#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 +#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 +#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 +#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 +#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 +#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 +#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 +#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 +#define FSYS1_NR_CLK 9 + +/* IMEM */ +#define IMEM_DMA0_IPCLKPORT_ACLK 1 +#define IMEM_DMA1_IPCLKPORT_ACLK 2 +#define IMEM_WDT0_IPCLKPORT_PCLK 3 +#define IMEM_WDT1_IPCLKPORT_PCLK 4 +#define IMEM_WDT2_IPCLKPORT_PCLK 5 +#define IMEM_MCT_PCLK 6 +#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 +#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 +#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 +#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 +#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 +#define IMEM_NR_CLK 12 + +/* MFC */ +#define MFC_MFC_IPCLKPORT_ACLK 1 +#define MFC_NR_CLK 2 + +/* CAM_CSI */ +#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 +#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 +#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 +#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 +#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 +#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 +#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 +#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 +#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 +#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 +#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 +#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_NR_CLK 13 +#endif /* _DT_BINDINGS_CLOCK_FSD_H */ -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Alim Akhtar <alim.akhtar@samsung.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar <alim.akhtar@samsung.com>, linux-fsd@tesla.com Subject: [PATCH 02/23] dt-bindings: clock: Add bindings definitions for FSD CMU blocks Date: Thu, 13 Jan 2022 17:41:22 +0530 [thread overview] Message-ID: <20220113121143.22280-3-alim.akhtar@samsung.com> (raw) In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> Clock controller driver of FSD platform is designed to have separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU block. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> --- include/dt-bindings/clock/fsd-clk.h | 146 ++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 include/dt-bindings/clock/fsd-clk.h diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h new file mode 100644 index 000000000000..9b97417ea6a1 --- /dev/null +++ b/include/dt-bindings/clock/fsd-clk.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * The constants defined in this header are being used in dts + * and fsd platform driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_FSD_H +#define _DT_BINDINGS_CLOCK_FSD_H + +/* CMU */ +#define DOUT_CMU_PLL_SHARED0_DIV4 1 +#define DOUT_CMU_PERIC_SHARED1DIV36 2 +#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 +#define DOUT_CMU_PERIC_SHARED0DIV20 4 +#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 +#define DOUT_CMU_PLL_SHARED0_DIV6 6 +#define DOUT_CMU_FSYS0_SHARED1DIV4 7 +#define DOUT_CMU_FSYS0_SHARED0DIV4 8 +#define DOUT_CMU_FSYS1_SHARED0DIV8 9 +#define DOUT_CMU_FSYS1_SHARED0DIV4 10 +#define CMU_CPUCL_SWITCH_GATE 11 +#define DOUT_CMU_IMEM_TCUCLK 12 +#define DOUT_CMU_IMEM_ACLK 13 +#define DOUT_CMU_IMEM_DMACLK 14 +#define GAT_CMU_FSYS0_SHARED0DIV4 15 +#define CMU_NR_CLK 16 + +/* PERIC */ +#define PERIC_SCLK_UART0 1 +#define PERIC_PCLK_UART0 2 +#define PERIC_SCLK_UART1 3 +#define PERIC_PCLK_UART1 4 +#define PERIC_DMA0_IPCLKPORT_ACLK 5 +#define PERIC_DMA1_IPCLKPORT_ACLK 6 +#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 +#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 +#define PERIC_PCLK_SPI0 9 +#define PERIC_SCLK_SPI0 10 +#define PERIC_PCLK_SPI1 11 +#define PERIC_SCLK_SPI1 12 +#define PERIC_PCLK_SPI2 13 +#define PERIC_SCLK_SPI2 14 +#define PERIC_PCLK_TDM0 15 +#define PERIC_PCLK_HSI2C0 16 +#define PERIC_PCLK_HSI2C1 17 +#define PERIC_PCLK_HSI2C2 18 +#define PERIC_PCLK_HSI2C3 19 +#define PERIC_PCLK_HSI2C4 20 +#define PERIC_PCLK_HSI2C5 21 +#define PERIC_PCLK_HSI2C6 22 +#define PERIC_PCLK_HSI2C7 23 +#define PERIC_MCAN0_IPCLKPORT_CCLK 24 +#define PERIC_MCAN0_IPCLKPORT_PCLK 25 +#define PERIC_MCAN1_IPCLKPORT_CCLK 26 +#define PERIC_MCAN1_IPCLKPORT_PCLK 27 +#define PERIC_MCAN2_IPCLKPORT_CCLK 28 +#define PERIC_MCAN2_IPCLKPORT_PCLK 29 +#define PERIC_MCAN3_IPCLKPORT_CCLK 30 +#define PERIC_MCAN3_IPCLKPORT_PCLK 31 +#define PERIC_PCLK_ADCIF 32 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 +#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 +#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 +#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 +#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 +#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 +#define PERIC_HCLK_TDM0 40 +#define PERIC_PCLK_TDM1 41 +#define PERIC_HCLK_TDM1 42 +#define PERIC_EQOS_PHYRXCLK_MUX 43 +#define PERIC_EQOS_PHYRXCLK 44 +#define PERIC_DOUT_RGMII_CLK 45 +#define PERIC_NR_CLK 46 + +/* FSYS0 */ +#define UFS0_MPHY_REFCLK_IXTAL24 1 +#define UFS0_MPHY_REFCLK_IXTAL26 2 +#define UFS1_MPHY_REFCLK_IXTAL24 3 +#define UFS1_MPHY_REFCLK_IXTAL26 4 +#define UFS0_TOP0_HCLK_BUS 5 +#define UFS0_TOP0_ACLK 6 +#define UFS0_TOP0_CLK_UNIPRO 7 +#define UFS0_TOP0_FMP_CLK 8 +#define UFS1_TOP1_HCLK_BUS 9 +#define UFS1_TOP1_ACLK 10 +#define UFS1_TOP1_CLK_UNIPRO 11 +#define UFS1_TOP1_FMP_CLK 12 +#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 +#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 +#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 +#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 +#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 +#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 +#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 +#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 +#define FSYS0_NR_CLK 23 + +/* FSYS1 */ +#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 +#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 +#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 +#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 +#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 +#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 +#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 +#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 +#define FSYS1_NR_CLK 9 + +/* IMEM */ +#define IMEM_DMA0_IPCLKPORT_ACLK 1 +#define IMEM_DMA1_IPCLKPORT_ACLK 2 +#define IMEM_WDT0_IPCLKPORT_PCLK 3 +#define IMEM_WDT1_IPCLKPORT_PCLK 4 +#define IMEM_WDT2_IPCLKPORT_PCLK 5 +#define IMEM_MCT_PCLK 6 +#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 +#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 +#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 +#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 +#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 +#define IMEM_NR_CLK 12 + +/* MFC */ +#define MFC_MFC_IPCLKPORT_ACLK 1 +#define MFC_NR_CLK 2 + +/* CAM_CSI */ +#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 +#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 +#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 +#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 +#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 +#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 +#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 +#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 +#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 +#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 +#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 +#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_NR_CLK 13 +#endif /* _DT_BINDINGS_CLOCK_FSD_H */ -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-01-13 12:23 UTC|newest] Thread overview: 159+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220113122302epcas5p1d45c0714fe286f8f91d0f28c3fad86e4@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 00/23] Add support for Tesla Full Self-Driving (FSD) SoC Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122311epcas5p4b7c253b49dce3bd3580407fcf312e70e@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 01/23] dt-bindings: clock: Document FSD CMU bindings Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:40 ` Krzysztof Kozlowski 2022-01-13 12:40 ` Krzysztof Kozlowski 2022-01-14 5:48 ` Alim Akhtar 2022-01-14 5:48 ` Alim Akhtar 2022-01-13 23:33 ` Rob Herring 2022-01-13 23:33 ` Rob Herring [not found] ` <CGME20220113122317epcas5p11937078e2701b319a13b29e044224ec0@epcas5p1.samsung.com> 2022-01-13 12:11 ` Alim Akhtar [this message] 2022-01-13 12:11 ` [PATCH 02/23] dt-bindings: clock: Add bindings definitions for FSD CMU blocks Alim Akhtar [not found] ` <CGME20220113122324epcas5p105c53b448b5801813a02a88c6107a2f3@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 03/23] clk: samsung: fsd: Add initial clock support Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:49 ` Krzysztof Kozlowski 2022-01-13 12:49 ` Krzysztof Kozlowski 2022-01-14 6:16 ` Alim Akhtar 2022-01-14 6:16 ` Alim Akhtar [not found] ` <CGME20220113122330epcas5p46ae5cd30950b1d9126479231dcf5da49@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 04/23] clk: samsung: fsd: Add cmu_peric block clock information Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:55 ` Krzysztof Kozlowski 2022-01-13 12:55 ` Krzysztof Kozlowski 2022-01-14 6:30 ` Alim Akhtar 2022-01-14 6:30 ` Alim Akhtar [not found] ` <CGME20220113122334epcas5p2d5958c77b0635e848f81ed2c5c98cdd5@epcas5p2.samsung.com> 2022-01-13 12:11 ` [PATCH 05/23] clk: samsung: fsd: Add cmu_fsys0 " Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122338epcas5p17ad3a31077b98388c0a6779904ee651e@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 06/23] clk: samsung: fsd: Add cmu_fsys1 " Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122343epcas5p23831143e4e8fb92be8ad362f4817c03b@epcas5p2.samsung.com> 2022-01-13 12:11 ` [PATCH 07/23] clk: samsung: fsd: Add cmu_imem block " Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122346epcas5p41a7d6712c07544e99795ef5465f1f106@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 08/23] clk: samsung: fsd: Add cmu_mfc " Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122351epcas5p45f49a559af9f6d0c6ba573594f95561d@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 09/23] clk: samsung: fsd: Add cam_csi " Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122354epcas5p19e5cebe9e85e9ba1758fa0b9d7d1ef75@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 10/23] dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:27 ` Krzysztof Kozlowski 2022-01-13 12:27 ` Krzysztof Kozlowski 2022-01-14 5:44 ` Alim Akhtar 2022-01-14 5:44 ` Alim Akhtar 2022-01-14 7:49 ` Krzysztof Kozlowski 2022-01-14 7:49 ` Krzysztof Kozlowski 2022-01-14 8:38 ` Alim Akhtar 2022-01-14 8:38 ` Alim Akhtar [not found] ` <CGME20220113122400epcas5p34363ba8f477b4c273d601d0b64324afa@epcas5p3.samsung.com> 2022-01-13 12:11 ` [PATCH 11/23] pinctrl: samsung: add FSD SoC specific data Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:57 ` Krzysztof Kozlowski 2022-01-13 12:57 ` Krzysztof Kozlowski 2022-01-16 12:05 ` Linus Walleij 2022-01-16 12:05 ` Linus Walleij [not found] ` <CGME20220113122404epcas5p4aa1c3ac09510eb55cce5fdd0791993a6@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 12/23] dt-bindings: add vendor prefix for Tesla Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:58 ` Krzysztof Kozlowski 2022-01-13 12:58 ` Krzysztof Kozlowski 2022-01-14 7:10 ` Alim Akhtar 2022-01-14 7:10 ` Alim Akhtar 2022-01-16 12:09 ` Linus Walleij 2022-01-16 12:09 ` Linus Walleij [not found] ` <CGME20220113122408epcas5p45053d1bf0acf2d8233a98b6c1abab6eb@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:33 ` Krzysztof Kozlowski 2022-01-13 12:33 ` Krzysztof Kozlowski 2022-01-14 16:57 ` Alim Akhtar 2022-01-14 16:57 ` Alim Akhtar 2022-01-14 17:29 ` Krzysztof Kozlowski 2022-01-14 17:29 ` Krzysztof Kozlowski 2022-01-17 13:26 ` Alim Akhtar 2022-01-17 13:26 ` Alim Akhtar 2022-01-17 14:14 ` Arnd Bergmann 2022-01-17 14:14 ` Arnd Bergmann 2022-01-17 15:00 ` Krzysztof Kozlowski 2022-01-17 15:00 ` Krzysztof Kozlowski 2022-01-17 20:41 ` Olof Johansson 2022-01-17 20:41 ` Olof Johansson [not found] ` <CGME20220113122413epcas5p46cb2cafb73936c423017240f98f72845@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 14/23] arm64: dts: fsd: Add initial device tree support Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:16 ` Krzysztof Kozlowski 2022-01-13 13:16 ` Krzysztof Kozlowski 2022-01-13 14:23 ` Arnd Bergmann 2022-01-13 14:23 ` Arnd Bergmann 2022-01-14 8:13 ` Alim Akhtar 2022-01-14 8:13 ` Alim Akhtar 2022-01-14 2:08 ` kernel test robot 2022-01-14 2:08 ` kernel test robot 2022-01-14 2:08 ` kernel test robot 2022-01-14 2:45 ` Rob Herring 2022-01-14 2:45 ` Rob Herring 2022-01-15 15:31 ` Alim Akhtar 2022-01-15 15:31 ` Alim Akhtar [not found] ` <CGME20220113122417epcas5p47398a5190cdf4c574c6f1762918b549f@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl support Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:19 ` Krzysztof Kozlowski 2022-01-13 13:19 ` Krzysztof Kozlowski 2022-01-17 13:44 ` Alim Akhtar 2022-01-17 13:44 ` Alim Akhtar 2022-01-17 13:50 ` Krzysztof Kozlowski 2022-01-17 13:50 ` Krzysztof Kozlowski 2022-01-18 14:58 ` Alim Akhtar 2022-01-18 14:58 ` Alim Akhtar [not found] ` <CGME20220113122421epcas5p1af8422fc992801ced57e0439b48ad08e@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 16/23] arm64: defconfig: Enable Tesla FSD SoC Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar [not found] ` <CGME20220113122427epcas5p1885d8b3b735e8f127b6694a309796e5a@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 17/23] Documentation: bindings: Add fsd spi compatible in dt-bindings document Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:21 ` Krzysztof Kozlowski 2022-01-13 13:21 ` Krzysztof Kozlowski 2022-01-13 13:24 ` Krzysztof Kozlowski 2022-01-13 13:24 ` Krzysztof Kozlowski 2022-01-14 7:17 ` Alim Akhtar 2022-01-14 7:17 ` Alim Akhtar [not found] ` <CGME20220113122435epcas5p18e6a2699f193b9e1287588278a570235@epcas5p1.samsung.com> 2022-01-13 12:11 ` [PATCH 18/23] spi: s3c64xx: Add spi port configuration for Tesla FSD SoC Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 12:59 ` Mark Brown 2022-01-13 12:59 ` Mark Brown 2022-01-14 7:15 ` Alim Akhtar 2022-01-14 7:15 ` Alim Akhtar 2022-01-13 13:28 ` Krzysztof Kozlowski 2022-01-13 13:28 ` Krzysztof Kozlowski 2022-01-16 12:12 ` Linus Walleij 2022-01-16 12:12 ` Linus Walleij [not found] ` <CGME20220113122440epcas5p4651d7cb2fc6d6a70fd5eaab5eadcf996@epcas5p4.samsung.com> 2022-01-13 12:11 ` [PATCH 19/23] arm64: dts: fsd: Add SPI device nodes Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:30 ` Krzysztof Kozlowski 2022-01-13 13:30 ` Krzysztof Kozlowski [not found] ` <CGME20220113122447epcas5p266d44c8df143229d22dfa700c285a786@epcas5p2.samsung.com> 2022-01-13 12:11 ` [PATCH 20/23] dt-bindings: iio: adc: exynos-adc: Add ADC-V3 variant Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:32 ` Krzysztof Kozlowski 2022-01-13 13:32 ` Krzysztof Kozlowski 2022-01-17 9:47 ` Jonathan Cameron 2022-01-17 9:47 ` Jonathan Cameron 2022-01-17 12:42 ` Alim Akhtar 2022-01-17 12:42 ` Alim Akhtar [not found] ` <CGME20220113122452epcas5p201a3a87d0e9c0e9f449a90ed62de1f1c@epcas5p2.samsung.com> 2022-01-13 12:11 ` [PATCH 21/23] iio: adc: exynos-adc: Add support for ADC V3 controller Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-16 11:19 ` Jonathan Cameron 2022-01-16 11:19 ` Jonathan Cameron 2022-01-17 12:20 ` Alim Akhtar 2022-01-17 12:20 ` Alim Akhtar [not found] ` <CGME20220113122456epcas5p35f6406ab03af58d2e56b0b7304d4d002@epcas5p3.samsung.com> 2022-01-13 12:11 ` [PATCH 22/23] arm64: dts: fsd: Add ADC device tree node Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:33 ` Krzysztof Kozlowski 2022-01-13 13:33 ` Krzysztof Kozlowski [not found] ` <CGME20220113122502epcas5p37747b0c5c242c0571d294b9245963a1c@epcas5p3.samsung.com> 2022-01-13 12:11 ` [PATCH 23/23] clocksource: exynos_mct: Add support for handling three clusters Alim Akhtar 2022-01-13 12:11 ` Alim Akhtar 2022-01-13 13:36 ` Krzysztof Kozlowski 2022-01-13 13:36 ` Krzysztof Kozlowski 2022-01-13 12:31 ` [PATCH 00/23] Add support for Tesla Full Self-Driving (FSD) SoC Krzysztof Kozlowski 2022-01-13 12:31 ` Krzysztof Kozlowski 2022-01-13 18:53 ` Olof Johansson 2022-01-13 18:53 ` Olof Johansson 2022-01-14 5:41 ` Alim Akhtar 2022-01-14 5:41 ` Alim Akhtar 2022-01-14 7:34 ` Krzysztof Kozlowski 2022-01-14 7:34 ` Krzysztof Kozlowski 2022-01-16 9:23 ` Pavel Machek 2022-01-16 9:23 ` Pavel Machek 2022-01-17 20:53 ` Olof Johansson 2022-01-17 20:53 ` Olof Johansson 2022-01-17 23:10 ` Pavel Machek 2022-01-17 23:10 ` Pavel Machek
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