From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v8 00/23] Support UXL filed in xstatus Date: Thu, 20 Jan 2022 20:20:27 +0800 [thread overview] Message-ID: <20220120122050.41546-1-zhiwei_liu@c-sky.com> (raw) In this patch set, we process the pc reigsters writes, gdb reads and writes, and address calculation under different UXLEN settings. The patch set v8 has been tested by running rv64 Linux with rv32 rootfs in compat mode. You can almost follow the test [1] given by GuoRen, except using the branch riscv-upstream-uxl-v8 on my QEMU repo [2]. [1] https://lore.kernel.org/linux-arm-kernel/20211228143958.3409187-17-guoren@kernel.org/t/ [2] https://github.com/romanheros/qemu.git Except patch 22 is new, the other patches have been reviewed or acked. v8: Set default XLEN for hypervisor vsstatus and mstatus_hs v7: Rebase to Alistair riscv_to_apply.next branch Add commit message for create xl field in CPURISCVState v6: Pass boot 32bit rootfs on compat Linux Pass test cases on compat OpenTee Fix csr write mask Fix WARL for uxl Fix sstatus read for uxl Relax UXL field for debugging Don't bump machine state version for xl Rename cpu_get_xl to cpu_recompute_xl Rebase to vector v1.0 Rebase to 128 bit cpu v5: Add xl field in env to clear up redundant riscv_cpu_xl Adjust pmpcfg access with mxl Select gdb core xml according to mxl v4: Support SSTATUS64_UXL write Bump vmstate version for vill split v3: Merge gen_pm_adjust_address into a canonical address function Adjust address for RVA with XLEN Split pm_enabled into pm_mask_enabled and pm_base_enabled Replace array of pm tcg globals with one scalar tcg global Split and change patch sequence v2: Split out vill from vtype Remove context switch when xlen changes at exception Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ld LIU Zhiwei (23): target/riscv: Adjust pmpcfg access with mxl target/riscv: Don't save pc when exception return target/riscv: Sign extend link reg for jal and jalr target/riscv: Sign extend pc for different XLEN target/riscv: Create xl field in env target/riscv: Ignore the pc bits above XLEN target/riscv: Extend pc for runtime pc write target/riscv: Use gdb xml according to max mxlen target/riscv: Relax debug check for pm write target/riscv: Adjust csr write mask with XLEN target/riscv: Create current pm fields in env target/riscv: Alloc tcg global for cur_pm[mask|base] target/riscv: Calculate address according to XLEN target/riscv: Split pm_enabled into mask and base target/riscv: Split out the vill from vtype target/riscv: Adjust vsetvl according to XLEN target/riscv: Remove VILL field in VTYPE target/riscv: Fix check range for first fault only target/riscv: Adjust vector address with mask target/riscv: Adjust scalar reg in vector with XLEN target/riscv: Set default XLEN for hypervisor target/riscv: Enable uxl field write target/riscv: Relax UXL field for debugging target/riscv/cpu.c | 42 +++++++-- target/riscv/cpu.h | 45 ++++++++- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 94 +++++++++---------- target/riscv/csr.c | 84 +++++++++++++++-- target/riscv/gdbstub.c | 71 ++++++++++---- target/riscv/helper.h | 4 +- .../riscv/insn_trans/trans_privileged.c.inc | 9 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +- target/riscv/insn_trans/trans_rvd.c.inc | 19 +--- target/riscv/insn_trans/trans_rvf.c.inc | 19 +--- target/riscv/insn_trans/trans_rvi.c.inc | 39 +++----- target/riscv/insn_trans/trans_rvv.c.inc | 6 +- target/riscv/machine.c | 16 +++- target/riscv/op_helper.c | 7 +- target/riscv/pmp.c | 12 +-- target/riscv/translate.c | 90 +++++++++--------- target/riscv/vector_helper.c | 39 +++++--- 18 files changed, 377 insertions(+), 231 deletions(-) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v8 00/23] Support UXL filed in xstatus Date: Thu, 20 Jan 2022 20:20:27 +0800 [thread overview] Message-ID: <20220120122050.41546-1-zhiwei_liu@c-sky.com> (raw) In this patch set, we process the pc reigsters writes, gdb reads and writes, and address calculation under different UXLEN settings. The patch set v8 has been tested by running rv64 Linux with rv32 rootfs in compat mode. You can almost follow the test [1] given by GuoRen, except using the branch riscv-upstream-uxl-v8 on my QEMU repo [2]. [1] https://lore.kernel.org/linux-arm-kernel/20211228143958.3409187-17-guoren@kernel.org/t/ [2] https://github.com/romanheros/qemu.git Except patch 22 is new, the other patches have been reviewed or acked. v8: Set default XLEN for hypervisor vsstatus and mstatus_hs v7: Rebase to Alistair riscv_to_apply.next branch Add commit message for create xl field in CPURISCVState v6: Pass boot 32bit rootfs on compat Linux Pass test cases on compat OpenTee Fix csr write mask Fix WARL for uxl Fix sstatus read for uxl Relax UXL field for debugging Don't bump machine state version for xl Rename cpu_get_xl to cpu_recompute_xl Rebase to vector v1.0 Rebase to 128 bit cpu v5: Add xl field in env to clear up redundant riscv_cpu_xl Adjust pmpcfg access with mxl Select gdb core xml according to mxl v4: Support SSTATUS64_UXL write Bump vmstate version for vill split v3: Merge gen_pm_adjust_address into a canonical address function Adjust address for RVA with XLEN Split pm_enabled into pm_mask_enabled and pm_base_enabled Replace array of pm tcg globals with one scalar tcg global Split and change patch sequence v2: Split out vill from vtype Remove context switch when xlen changes at exception Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ld LIU Zhiwei (23): target/riscv: Adjust pmpcfg access with mxl target/riscv: Don't save pc when exception return target/riscv: Sign extend link reg for jal and jalr target/riscv: Sign extend pc for different XLEN target/riscv: Create xl field in env target/riscv: Ignore the pc bits above XLEN target/riscv: Extend pc for runtime pc write target/riscv: Use gdb xml according to max mxlen target/riscv: Relax debug check for pm write target/riscv: Adjust csr write mask with XLEN target/riscv: Create current pm fields in env target/riscv: Alloc tcg global for cur_pm[mask|base] target/riscv: Calculate address according to XLEN target/riscv: Split pm_enabled into mask and base target/riscv: Split out the vill from vtype target/riscv: Adjust vsetvl according to XLEN target/riscv: Remove VILL field in VTYPE target/riscv: Fix check range for first fault only target/riscv: Adjust vector address with mask target/riscv: Adjust scalar reg in vector with XLEN target/riscv: Set default XLEN for hypervisor target/riscv: Enable uxl field write target/riscv: Relax UXL field for debugging target/riscv/cpu.c | 42 +++++++-- target/riscv/cpu.h | 45 ++++++++- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 94 +++++++++---------- target/riscv/csr.c | 84 +++++++++++++++-- target/riscv/gdbstub.c | 71 ++++++++++---- target/riscv/helper.h | 4 +- .../riscv/insn_trans/trans_privileged.c.inc | 9 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +- target/riscv/insn_trans/trans_rvd.c.inc | 19 +--- target/riscv/insn_trans/trans_rvf.c.inc | 19 +--- target/riscv/insn_trans/trans_rvi.c.inc | 39 +++----- target/riscv/insn_trans/trans_rvv.c.inc | 6 +- target/riscv/machine.c | 16 +++- target/riscv/op_helper.c | 7 +- target/riscv/pmp.c | 12 +-- target/riscv/translate.c | 90 +++++++++--------- target/riscv/vector_helper.c | 39 +++++--- 18 files changed, 377 insertions(+), 231 deletions(-) -- 2.25.1
next reply other threads:[~2022-01-20 15:54 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-20 12:20 LIU Zhiwei [this message] 2022-01-20 12:20 ` [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 15/23] target/riscv: Split out the vill from vtype LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 19/23] target/riscv: Adjust vector address with mask LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 21:25 ` Alistair Francis 2022-01-20 21:25 ` Alistair Francis 2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis 2022-01-21 0:03 ` Alistair Francis
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