From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE Date: Thu, 20 Jan 2022 20:20:44 +0800 [thread overview] Message-ID: <20220120122050.41546-18-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe58ccaeae..55635d68d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,7 +111,6 @@ FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE Date: Thu, 20 Jan 2022 20:20:44 +0800 [thread overview] Message-ID: <20220120122050.41546-18-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe58ccaeae..55635d68d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,7 +111,6 @@ FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; -- 2.25.1
next prev parent reply other threads:[~2022-01-20 17:33 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-20 12:20 [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 15/23] target/riscv: Split out the vill from vtype LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei [this message] 2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 19/23] target/riscv: Adjust vector address with mask LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 21:25 ` Alistair Francis 2022-01-20 21:25 ` Alistair Francis 2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei 2022-01-20 12:20 ` LIU Zhiwei 2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis 2022-01-21 0:03 ` Alistair Francis
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220120122050.41546-18-zhiwei_liu@c-sky.com \ --to=zhiwei_liu@c-sky.com \ --cc=alistair.francis@wdc.com \ --cc=bin.meng@windriver.com \ --cc=guoren@linux.alibaba.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.