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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>,
	Anup Patel <anup.patel@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Date: Fri, 21 Jan 2022 15:57:40 +1000	[thread overview]
Message-ID: <20220121055830.3164408-12-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com>

From: Yifei Jiang <jiangyifei@huawei.com>

Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-9-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
 target/riscv/kvm.c                 | 42 ++++++++++++++++-
 2 files changed, 113 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/sbi_ecall_interface.h

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
new file mode 100644
index 0000000000..fb1a3fa8f2
--- /dev/null
+++ b/target/riscv/sbi_ecall_interface.h
@@ -0,0 +1,72 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_ECALL_INTERFACE_H__
+#define __SBI_ECALL_INTERFACE_H__
+
+/* clang-format off */
+
+/* SBI Extension IDs */
+#define SBI_EXT_0_1_SET_TIMER           0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR     0x2
+#define SBI_EXT_0_1_CLEAR_IPI           0x3
+#define SBI_EXT_0_1_SEND_IPI            0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I      0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA   0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN            0x8
+#define SBI_EXT_BASE                    0x10
+#define SBI_EXT_TIME                    0x54494D45
+#define SBI_EXT_IPI                     0x735049
+#define SBI_EXT_RFENCE                  0x52464E43
+#define SBI_EXT_HSM                     0x48534D
+
+/* SBI function IDs for BASE extension*/
+#define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
+#define SBI_EXT_BASE_GET_IMP_ID         0x1
+#define SBI_EXT_BASE_GET_IMP_VERSION    0x2
+#define SBI_EXT_BASE_PROBE_EXT          0x3
+#define SBI_EXT_BASE_GET_MVENDORID      0x4
+#define SBI_EXT_BASE_GET_MARCHID        0x5
+#define SBI_EXT_BASE_GET_MIMPID         0x6
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER          0x0
+
+/* SBI function IDs for IPI extension*/
+#define SBI_EXT_IPI_SEND_IPI            0x0
+
+/* SBI function IDs for RFENCE extension*/
+#define SBI_EXT_RFENCE_REMOTE_FENCE_I       0x0
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA    0x1
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID  0x2
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA   0x3
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA   0x5
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
+
+/* SBI function IDs for HSM extension */
+#define SBI_EXT_HSM_HART_START          0x0
+#define SBI_EXT_HSM_HART_STOP           0x1
+#define SBI_EXT_HSM_HART_GET_STATUS     0x2
+
+#define SBI_HSM_HART_STATUS_STARTED     0x0
+#define SBI_HSM_HART_STATUS_STOPPED     0x1
+#define SBI_HSM_HART_STATUS_START_PENDING   0x2
+#define SBI_HSM_HART_STATUS_STOP_PENDING    0x3
+
+#define SBI_SPEC_VERSION_MAJOR_OFFSET   24
+#define SBI_SPEC_VERSION_MAJOR_MASK     0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK     0xffffff
+#define SBI_EXT_VENDOR_START            0x09000000
+#define SBI_EXT_VENDOR_END              0x09FFFFFF
+/* clang-format on */
+
+#endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0ba64795d5..e90e2a6709 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,8 @@
 #include "qemu/log.h"
 #include "hw/loader.h"
 #include "kvm_riscv.h"
+#include "sbi_ecall_interface.h"
+#include "chardev/char-fe.h"
 
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
@@ -367,9 +369,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+{
+    int ret = 0;
+    unsigned char ch;
+    switch (run->riscv_sbi.extension_id) {
+    case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+        ch = run->riscv_sbi.args[0];
+        qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+        break;
+    case SBI_EXT_0_1_CONSOLE_GETCHAR:
+        ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+        if (ret == sizeof(ch)) {
+            run->riscv_sbi.args[0] = ch;
+        } else {
+            run->riscv_sbi.args[0] = -1;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+                      __func__, run->riscv_sbi.extension_id);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
-    return 0;
+    int ret = 0;
+    switch (run->exit_reason) {
+    case KVM_EXIT_RISCV_SBI:
+        ret = kvm_riscv_handle_sbi(cs, run);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                      __func__, run->exit_reason);
+        ret = -1;
+        break;
+    }
+    return ret;
 }
 
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-- 
2.31.1



  parent reply	other threads:[~2022-01-21  6:31 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-21  5:57 [PULL 00/61] riscv-to-apply queue Alistair Francis
2022-01-21  5:57 ` [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register Alistair Francis
2022-01-21  5:57 ` [PULL 02/61] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-21  5:57 ` [PULL 03/61] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-21  5:57 ` [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2022-01-21  5:57 ` [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Alistair Francis
2022-01-21  5:57 ` [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu Alistair Francis
2022-01-21  5:57 ` [PULL 07/61] target/riscv: Implement kvm_arch_get_registers Alistair Francis
2022-01-21  5:57 ` [PULL 08/61] target/riscv: Implement kvm_arch_put_registers Alistair Francis
2022-01-21  5:57 ` [PULL 09/61] target/riscv: Support start kernel directly by KVM Alistair Francis
2022-01-21  5:57 ` [PULL 10/61] target/riscv: Support setting external interrupt " Alistair Francis
2022-01-21  5:57 ` Alistair Francis [this message]
2022-01-21  5:57 ` [PULL 12/61] target/riscv: Add host cpu type Alistair Francis
2022-01-21  5:57 ` [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer Alistair Francis
2022-01-21  5:57 ` [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing Alistair Francis
2022-01-21  5:57 ` [PULL 15/61] target/riscv: Support virtual time context synchronization Alistair Francis
2022-01-21  5:57 ` [PULL 16/61] target/riscv: enable riscv kvm accel Alistair Francis
2022-01-21  5:57 ` [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers Alistair Francis
2022-01-21  5:57 ` [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment Alistair Francis
2022-01-21  5:57 ` [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Alistair Francis
2022-01-21  5:57 ` [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Alistair Francis
2022-01-21  5:57 ` [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Alistair Francis
2022-01-21  5:57 ` [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Alistair Francis
2022-01-21  5:57 ` [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Alistair Francis
2022-01-21  5:57 ` [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Alistair Francis
2022-01-21  5:57 ` [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Alistair Francis
2022-01-21  5:57 ` [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Alistair Francis
2022-01-21  5:57 ` [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing " Alistair Francis
2022-01-21  5:57 ` [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Alistair Francis
2022-01-21  5:57 ` [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Alistair Francis
2022-01-21  5:57 ` [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Alistair Francis
2022-01-21  5:58 ` [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Alistair Francis
2022-01-21  5:58 ` [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Alistair Francis
2022-01-21  5:58 ` [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Alistair Francis
2022-01-21  5:58 ` [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing " Alistair Francis
2022-01-21  5:58 ` [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Alistair Francis
2022-01-21  5:58 ` [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios Alistair Francis
2022-01-21  5:58 ` [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names Alistair Francis
2022-01-21  5:58 ` [PULL 38/61] roms/opensbi: Remove ELF images Alistair Francis
2022-01-21  5:58 ` [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl Alistair Francis
2022-01-21  5:58 ` [PULL 40/61] target/riscv: Don't save pc when exception return Alistair Francis
2022-01-21  5:58 ` [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr Alistair Francis
2022-01-21  5:58 ` [PULL 42/61] target/riscv: Sign extend pc for different XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 43/61] target/riscv: Create xl field in env Alistair Francis
2022-01-21  5:58 ` [PULL 44/61] target/riscv: Ignore the pc bits above XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 45/61] target/riscv: Extend pc for runtime pc write Alistair Francis
2022-01-21  5:58 ` [PULL 46/61] target/riscv: Use gdb xml according to max mxlen Alistair Francis
2022-01-21  5:58 ` [PULL 47/61] target/riscv: Relax debug check for pm write Alistair Francis
2022-01-21  5:58 ` [PULL 48/61] target/riscv: Adjust csr write mask with XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 49/61] target/riscv: Create current pm fields in env Alistair Francis
2022-01-21  5:58 ` [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base] Alistair Francis
2022-01-21  5:58 ` [PULL 51/61] target/riscv: Calculate address according to XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 52/61] target/riscv: Split pm_enabled into mask and base Alistair Francis
2022-01-21  5:58 ` [PULL 53/61] target/riscv: Split out the vill from vtype Alistair Francis
2022-01-28 16:10   ` Peter Maydell
2022-02-01  2:12     ` Alistair Francis
2022-02-01  6:47       ` LIU Zhiwei
2022-01-21  5:58 ` [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 55/61] target/riscv: Remove VILL field in VTYPE Alistair Francis
2022-01-21  5:58 ` [PULL 56/61] target/riscv: Fix check range for first fault only Alistair Francis
2022-01-21  5:58 ` [PULL 57/61] target/riscv: Adjust vector address with mask Alistair Francis
2022-01-21  5:58 ` [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 59/61] target/riscv: Set default XLEN for hypervisor Alistair Francis
2022-01-21  5:58 ` [PULL 60/61] target/riscv: Enable uxl field write Alistair Francis
2022-01-21  5:58 ` [PULL 61/61] target/riscv: Relax UXL field for debugging Alistair Francis
2022-01-21 12:58 ` [PULL 00/61] riscv-to-apply queue Peter Maydell

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