From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Bin Meng" <bmeng.cn@gmail.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register
Date: Fri, 21 Jan 2022 15:57:30 +1000 [thread overview]
Message-ID: <20220121055830.3164408-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com>
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/timer/ibex_timer.h | 1 -
hw/timer/ibex_timer.c | 14 +++++---------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index b6f69b38ee..1a0a28d5fa 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -43,7 +43,6 @@ struct IbexTimerState {
uint32_t timer_compare_upper0;
uint32_t timer_intr_enable;
uint32_t timer_intr_state;
- uint32_t timer_intr_test;
uint32_t timebase_freq;
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index 66e1f8e48c..826c38b653 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -130,7 +130,6 @@ static void ibex_timer_reset(DeviceState *dev)
s->timer_compare_upper0 = 0xFFFFFFFF;
s->timer_intr_enable = 0x00000000;
s->timer_intr_state = 0x00000000;
- s->timer_intr_test = 0x00000000;
ibex_timer_update_irqs(s);
}
@@ -168,7 +167,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
retvalue = s->timer_intr_state;
break;
case R_INTR_TEST:
- retvalue = s->timer_intr_test;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempted to read INTR_TEST, a write only register");
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
@@ -215,10 +215,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
s->timer_intr_state &= ~val;
break;
case R_INTR_TEST:
- s->timer_intr_test = val;
- if (s->timer_intr_enable &
- s->timer_intr_test &
- R_INTR_ENABLE_IE_0_MASK) {
+ if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
@@ -247,8 +244,8 @@ static int ibex_timer_post_load(void *opaque, int version_id)
static const VMStateDescription vmstate_ibex_timer = {
.name = TYPE_IBEX_TIMER,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.post_load = ibex_timer_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(timer_ctrl, IbexTimerState),
@@ -257,7 +254,6 @@ static const VMStateDescription vmstate_ibex_timer = {
VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
VMSTATE_UINT32(timer_intr_state, IbexTimerState),
- VMSTATE_UINT32(timer_intr_test, IbexTimerState),
VMSTATE_END_OF_LIST()
}
};
--
2.31.1
next prev parent reply other threads:[~2022-01-21 6:09 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-21 5:57 [PULL 00/61] riscv-to-apply queue Alistair Francis
2022-01-21 5:57 ` Alistair Francis [this message]
2022-01-21 5:57 ` [PULL 02/61] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-21 5:57 ` [PULL 03/61] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-21 5:57 ` [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2022-01-21 5:57 ` [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Alistair Francis
2022-01-21 5:57 ` [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu Alistair Francis
2022-01-21 5:57 ` [PULL 07/61] target/riscv: Implement kvm_arch_get_registers Alistair Francis
2022-01-21 5:57 ` [PULL 08/61] target/riscv: Implement kvm_arch_put_registers Alistair Francis
2022-01-21 5:57 ` [PULL 09/61] target/riscv: Support start kernel directly by KVM Alistair Francis
2022-01-21 5:57 ` [PULL 10/61] target/riscv: Support setting external interrupt " Alistair Francis
2022-01-21 5:57 ` [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Alistair Francis
2022-01-21 5:57 ` [PULL 12/61] target/riscv: Add host cpu type Alistair Francis
2022-01-21 5:57 ` [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer Alistair Francis
2022-01-21 5:57 ` [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing Alistair Francis
2022-01-21 5:57 ` [PULL 15/61] target/riscv: Support virtual time context synchronization Alistair Francis
2022-01-21 5:57 ` [PULL 16/61] target/riscv: enable riscv kvm accel Alistair Francis
2022-01-21 5:57 ` [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers Alistair Francis
2022-01-21 5:57 ` [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment Alistair Francis
2022-01-21 5:57 ` [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Alistair Francis
2022-01-21 5:57 ` [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Alistair Francis
2022-01-21 5:57 ` [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Alistair Francis
2022-01-21 5:57 ` [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Alistair Francis
2022-01-21 5:57 ` [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Alistair Francis
2022-01-21 5:57 ` [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:57 ` [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Alistair Francis
2022-01-21 5:57 ` [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing " Alistair Francis
2022-01-21 5:57 ` [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Alistair Francis
2022-01-21 5:57 ` [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Alistair Francis
2022-01-21 5:58 ` [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Alistair Francis
2022-01-21 5:58 ` [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:58 ` [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Alistair Francis
2022-01-21 5:58 ` [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing " Alistair Francis
2022-01-21 5:58 ` [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Alistair Francis
2022-01-21 5:58 ` [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios Alistair Francis
2022-01-21 5:58 ` [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names Alistair Francis
2022-01-21 5:58 ` [PULL 38/61] roms/opensbi: Remove ELF images Alistair Francis
2022-01-21 5:58 ` [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl Alistair Francis
2022-01-21 5:58 ` [PULL 40/61] target/riscv: Don't save pc when exception return Alistair Francis
2022-01-21 5:58 ` [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr Alistair Francis
2022-01-21 5:58 ` [PULL 42/61] target/riscv: Sign extend pc for different XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 43/61] target/riscv: Create xl field in env Alistair Francis
2022-01-21 5:58 ` [PULL 44/61] target/riscv: Ignore the pc bits above XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 45/61] target/riscv: Extend pc for runtime pc write Alistair Francis
2022-01-21 5:58 ` [PULL 46/61] target/riscv: Use gdb xml according to max mxlen Alistair Francis
2022-01-21 5:58 ` [PULL 47/61] target/riscv: Relax debug check for pm write Alistair Francis
2022-01-21 5:58 ` [PULL 48/61] target/riscv: Adjust csr write mask with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 49/61] target/riscv: Create current pm fields in env Alistair Francis
2022-01-21 5:58 ` [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base] Alistair Francis
2022-01-21 5:58 ` [PULL 51/61] target/riscv: Calculate address according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 52/61] target/riscv: Split pm_enabled into mask and base Alistair Francis
2022-01-21 5:58 ` [PULL 53/61] target/riscv: Split out the vill from vtype Alistair Francis
2022-01-28 16:10 ` Peter Maydell
2022-02-01 2:12 ` Alistair Francis
2022-02-01 6:47 ` LIU Zhiwei
2022-01-21 5:58 ` [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 55/61] target/riscv: Remove VILL field in VTYPE Alistair Francis
2022-01-21 5:58 ` [PULL 56/61] target/riscv: Fix check range for first fault only Alistair Francis
2022-01-21 5:58 ` [PULL 57/61] target/riscv: Adjust vector address with mask Alistair Francis
2022-01-21 5:58 ` [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 59/61] target/riscv: Set default XLEN for hypervisor Alistair Francis
2022-01-21 5:58 ` [PULL 60/61] target/riscv: Enable uxl field write Alistair Francis
2022-01-21 5:58 ` [PULL 61/61] target/riscv: Relax UXL field for debugging Alistair Francis
2022-01-21 12:58 ` [PULL 00/61] riscv-to-apply queue Peter Maydell
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