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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, LIU Zhiwei <zhiwei_liu@c-sky.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 42/61] target/riscv: Sign extend pc for different XLEN
Date: Fri, 21 Jan 2022 15:58:11 +1000	[thread overview]
Message-ID: <20220121055830.3164408-43-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com>

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                      | 25 ++++++++++++++++---
 .../riscv/insn_trans/trans_privileged.c.inc   |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |  5 ++--
 target/riscv/insn_trans/trans_rvv.c.inc       |  4 +--
 4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 30c0e28778..2a88bd99dc 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -193,16 +193,33 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 }
 
+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        dest = (int32_t)dest;
+    }
+    tcg_gen_movi_tl(cpu_pc, dest);
+}
+
+static void gen_set_pc(DisasContext *ctx, TCGv dest)
+{
+    if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32s_tl(cpu_pc, dest);
+    } else {
+        tcg_gen_mov_tl(cpu_pc, dest);
+    }
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_set_pc_imm(ctx, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -225,10 +242,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
     if (translator_use_goto_tb(&ctx->base, dest)) {
         tcg_gen_goto_tb(n);
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
-        tcg_gen_movi_tl(cpu_pc, dest);
+        gen_set_pc_imm(ctx, dest);
         tcg_gen_lookup_and_goto_ptr();
     }
 }
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 6077bbbf11..53613682e8 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -102,7 +102,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     gen_helper_wfi(cpu_env);
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index b9ba57f266..04d3ea237f 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -59,6 +59,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
+    gen_set_pc(ctx, cpu_pc);
     if (!has_ext(ctx, RVC)) {
         TCGv t0 = tcg_temp_new();
 
@@ -827,7 +828,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * FENCE_I is a no-op in QEMU,
      * however we need to end the translation block
      */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -836,7 +837,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 static bool do_csr_post(DisasContext *ctx)
 {
     /* We may have changed important cpu state -- exit to main loop. */
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
     tcg_gen_exit_tb(NULL, 0);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7a040b3089..e03959c46f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -194,7 +194,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
 
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
@@ -219,7 +219,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
-    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+    gen_set_pc_imm(s, s->pc_succ_insn);
     tcg_gen_lookup_and_goto_ptr();
     s->base.is_jmp = DISAS_NORETURN;
 
-- 
2.31.1



  parent reply	other threads:[~2022-01-21  8:30 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-21  5:57 [PULL 00/61] riscv-to-apply queue Alistair Francis
2022-01-21  5:57 ` [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register Alistair Francis
2022-01-21  5:57 ` [PULL 02/61] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-21  5:57 ` [PULL 03/61] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-21  5:57 ` [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2022-01-21  5:57 ` [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Alistair Francis
2022-01-21  5:57 ` [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu Alistair Francis
2022-01-21  5:57 ` [PULL 07/61] target/riscv: Implement kvm_arch_get_registers Alistair Francis
2022-01-21  5:57 ` [PULL 08/61] target/riscv: Implement kvm_arch_put_registers Alistair Francis
2022-01-21  5:57 ` [PULL 09/61] target/riscv: Support start kernel directly by KVM Alistair Francis
2022-01-21  5:57 ` [PULL 10/61] target/riscv: Support setting external interrupt " Alistair Francis
2022-01-21  5:57 ` [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Alistair Francis
2022-01-21  5:57 ` [PULL 12/61] target/riscv: Add host cpu type Alistair Francis
2022-01-21  5:57 ` [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer Alistair Francis
2022-01-21  5:57 ` [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing Alistair Francis
2022-01-21  5:57 ` [PULL 15/61] target/riscv: Support virtual time context synchronization Alistair Francis
2022-01-21  5:57 ` [PULL 16/61] target/riscv: enable riscv kvm accel Alistair Francis
2022-01-21  5:57 ` [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers Alistair Francis
2022-01-21  5:57 ` [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment Alistair Francis
2022-01-21  5:57 ` [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Alistair Francis
2022-01-21  5:57 ` [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Alistair Francis
2022-01-21  5:57 ` [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Alistair Francis
2022-01-21  5:57 ` [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Alistair Francis
2022-01-21  5:57 ` [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Alistair Francis
2022-01-21  5:57 ` [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Alistair Francis
2022-01-21  5:57 ` [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Alistair Francis
2022-01-21  5:57 ` [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Alistair Francis
2022-01-21  5:57 ` [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing " Alistair Francis
2022-01-21  5:57 ` [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Alistair Francis
2022-01-21  5:57 ` [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Alistair Francis
2022-01-21  5:57 ` [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Alistair Francis
2022-01-21  5:58 ` [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Alistair Francis
2022-01-21  5:58 ` [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Alistair Francis
2022-01-21  5:58 ` [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Alistair Francis
2022-01-21  5:58 ` [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing " Alistair Francis
2022-01-21  5:58 ` [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Alistair Francis
2022-01-21  5:58 ` [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios Alistair Francis
2022-01-21  5:58 ` [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names Alistair Francis
2022-01-21  5:58 ` [PULL 38/61] roms/opensbi: Remove ELF images Alistair Francis
2022-01-21  5:58 ` [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl Alistair Francis
2022-01-21  5:58 ` [PULL 40/61] target/riscv: Don't save pc when exception return Alistair Francis
2022-01-21  5:58 ` [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr Alistair Francis
2022-01-21  5:58 ` Alistair Francis [this message]
2022-01-21  5:58 ` [PULL 43/61] target/riscv: Create xl field in env Alistair Francis
2022-01-21  5:58 ` [PULL 44/61] target/riscv: Ignore the pc bits above XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 45/61] target/riscv: Extend pc for runtime pc write Alistair Francis
2022-01-21  5:58 ` [PULL 46/61] target/riscv: Use gdb xml according to max mxlen Alistair Francis
2022-01-21  5:58 ` [PULL 47/61] target/riscv: Relax debug check for pm write Alistair Francis
2022-01-21  5:58 ` [PULL 48/61] target/riscv: Adjust csr write mask with XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 49/61] target/riscv: Create current pm fields in env Alistair Francis
2022-01-21  5:58 ` [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base] Alistair Francis
2022-01-21  5:58 ` [PULL 51/61] target/riscv: Calculate address according to XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 52/61] target/riscv: Split pm_enabled into mask and base Alistair Francis
2022-01-21  5:58 ` [PULL 53/61] target/riscv: Split out the vill from vtype Alistair Francis
2022-01-28 16:10   ` Peter Maydell
2022-02-01  2:12     ` Alistair Francis
2022-02-01  6:47       ` LIU Zhiwei
2022-01-21  5:58 ` [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 55/61] target/riscv: Remove VILL field in VTYPE Alistair Francis
2022-01-21  5:58 ` [PULL 56/61] target/riscv: Fix check range for first fault only Alistair Francis
2022-01-21  5:58 ` [PULL 57/61] target/riscv: Adjust vector address with mask Alistair Francis
2022-01-21  5:58 ` [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN Alistair Francis
2022-01-21  5:58 ` [PULL 59/61] target/riscv: Set default XLEN for hypervisor Alistair Francis
2022-01-21  5:58 ` [PULL 60/61] target/riscv: Enable uxl field write Alistair Francis
2022-01-21  5:58 ` [PULL 61/61] target/riscv: Relax UXL field for debugging Alistair Francis
2022-01-21 12:58 ` [PULL 00/61] riscv-to-apply queue Peter Maydell

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