From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v5 04/14] riscv: implement module alternatives Date: Fri, 21 Jan 2022 17:36:08 +0100 [thread overview] Message-ID: <20220121163618.351934-5-heiko@sntech.de> (raw) In-Reply-To: <20220121163618.351934-1-heiko@sntech.de> This allows alternatives to also be applied when loading modules and follows the implementation of other architectures (e.g. arm64). Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/alternative.h | 3 ++- arch/riscv/kernel/alternative.c | 16 ++++++++++++--- arch/riscv/kernel/module.c | 29 ++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 811bdd8027db..f0657b1b3174 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -18,8 +18,10 @@ #include <asm/hwcap.h> #define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */ +#define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */ void __init apply_boot_alternatives(void); +void apply_module_alternatives(void *start, size_t length); struct alt_entry { void *old_ptr; /* address of original instruciton or data */ @@ -37,6 +39,5 @@ struct errata_checkfunc_id { void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); - #endif #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index ead00c508266..e1849faa2fa1 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -7,6 +7,7 @@ */ #include <linux/init.h> +#include <linux/module.h> #include <linux/cpu.h> #include <linux/uaccess.h> #include <asm/alternative.h> @@ -58,9 +59,9 @@ static void __init init_alternative(void) * a feature detect on the boot CPU). No need to worry about other CPUs * here. */ -static void __init _apply_alternatives(struct alt_entry *begin, - struct alt_entry *end, - unsigned int stage) +static void __init_or_module _apply_alternatives(struct alt_entry *begin, + struct alt_entry *end, + unsigned int stage) { if (!vendor_patch_func) return; @@ -81,3 +82,12 @@ void __init apply_boot_alternatives(void) (struct alt_entry *)__alt_end, RISCV_ALTERNATIVES_BOOT); } + +#ifdef CONFIG_MODULES +void apply_module_alternatives(void *start, size_t length) +{ + _apply_alternatives((struct alt_entry *)start, + (struct alt_entry *)(start + length), + RISCV_ALTERNATIVES_MODULE); +} +#endif diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 68a9e3d1fe16..a778abd5b8b9 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -11,6 +11,7 @@ #include <linux/vmalloc.h> #include <linux/sizes.h> #include <linux/pgtable.h> +#include <asm/alternative.h> #include <asm/sections.h> static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v) @@ -416,3 +417,31 @@ void *module_alloc(unsigned long size) __builtin_return_address(0)); } #endif + +static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + const char *name) +{ + const Elf_Shdr *s, *se; + const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + + for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { + if (strcmp(name, secstrs + s->sh_name) == 0) + return s; + } + + return NULL; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *me) +{ + const Elf_Shdr *s; + + s = find_section(hdr, sechdrs, ".alternative"); + if (s) + apply_module_alternatives((void *)s->sh_addr, s->sh_size); + + return 0; +} -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v5 04/14] riscv: implement module alternatives Date: Fri, 21 Jan 2022 17:36:08 +0100 [thread overview] Message-ID: <20220121163618.351934-5-heiko@sntech.de> (raw) In-Reply-To: <20220121163618.351934-1-heiko@sntech.de> This allows alternatives to also be applied when loading modules and follows the implementation of other architectures (e.g. arm64). Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/alternative.h | 3 ++- arch/riscv/kernel/alternative.c | 16 ++++++++++++--- arch/riscv/kernel/module.c | 29 ++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 811bdd8027db..f0657b1b3174 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -18,8 +18,10 @@ #include <asm/hwcap.h> #define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */ +#define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */ void __init apply_boot_alternatives(void); +void apply_module_alternatives(void *start, size_t length); struct alt_entry { void *old_ptr; /* address of original instruciton or data */ @@ -37,6 +39,5 @@ struct errata_checkfunc_id { void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); - #endif #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index ead00c508266..e1849faa2fa1 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -7,6 +7,7 @@ */ #include <linux/init.h> +#include <linux/module.h> #include <linux/cpu.h> #include <linux/uaccess.h> #include <asm/alternative.h> @@ -58,9 +59,9 @@ static void __init init_alternative(void) * a feature detect on the boot CPU). No need to worry about other CPUs * here. */ -static void __init _apply_alternatives(struct alt_entry *begin, - struct alt_entry *end, - unsigned int stage) +static void __init_or_module _apply_alternatives(struct alt_entry *begin, + struct alt_entry *end, + unsigned int stage) { if (!vendor_patch_func) return; @@ -81,3 +82,12 @@ void __init apply_boot_alternatives(void) (struct alt_entry *)__alt_end, RISCV_ALTERNATIVES_BOOT); } + +#ifdef CONFIG_MODULES +void apply_module_alternatives(void *start, size_t length) +{ + _apply_alternatives((struct alt_entry *)start, + (struct alt_entry *)(start + length), + RISCV_ALTERNATIVES_MODULE); +} +#endif diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 68a9e3d1fe16..a778abd5b8b9 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -11,6 +11,7 @@ #include <linux/vmalloc.h> #include <linux/sizes.h> #include <linux/pgtable.h> +#include <asm/alternative.h> #include <asm/sections.h> static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v) @@ -416,3 +417,31 @@ void *module_alloc(unsigned long size) __builtin_return_address(0)); } #endif + +static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + const char *name) +{ + const Elf_Shdr *s, *se; + const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + + for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { + if (strcmp(name, secstrs + s->sh_name) == 0) + return s; + } + + return NULL; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *me) +{ + const Elf_Shdr *s; + + s = find_section(hdr, sechdrs, ".alternative"); + if (s) + apply_module_alternatives((void *)s->sh_addr, s->sh_size); + + return 0; +} -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-01-21 16:37 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-21 16:36 [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 01/14] riscv: only use IPIs to handle cache-flushes on remote cpus Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-22 3:45 ` Atish Patra 2022-01-22 3:45 ` Atish Patra 2022-01-24 12:30 ` Heiko Stübner 2022-01-24 12:30 ` Heiko Stübner 2022-01-22 4:10 ` Anup Patel 2022-01-22 4:10 ` Anup Patel 2022-01-21 16:36 ` [PATCH v5 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 03/14] riscv: allow different stages with alternatives Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner [this message] 2022-01-21 16:36 ` [PATCH v5 04/14] riscv: implement module alternatives Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 08/14] riscv: move boot alternatives to a slightly earlier position Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-02-04 22:33 ` Rob Herring 2022-02-04 22:33 ` Rob Herring 2022-02-07 13:39 ` Heiko Stuebner 2022-02-07 13:39 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 12/14] riscv: add RISC-V Svpbmt extension supports Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-21 16:36 ` [PATCH v5 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner 2022-01-21 16:36 ` Heiko Stuebner 2022-01-24 7:22 ` [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types Christoph Hellwig 2022-01-24 7:22 ` Christoph Hellwig
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