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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 16/27] memory: renesas-rpc-if: Add support for RZ/G2L
Date: Mon, 31 Jan 2022 12:18:52 +0000	[thread overview]
Message-ID: <20220131121903.8620-17-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20220131121903.8620-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

commit b04cc0d912eb80d3c438b11d96ca847c3e77e8ab upstream.

SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to
the RPC-IF interface found on R-Car Gen3 SoC's.

This patch adds a new compatible string for the RZ/G2L family so
that the timing values on RZ/G2L can be adjusted.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211025205631.21151-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/memory/renesas-rpc-if.c | 72 ++++++++++++++++++++++++++++-----
 drivers/mtd/hyperbus/rpc-if.c   |  4 +-
 drivers/spi/spi-rpc-if.c        |  4 +-
 include/memory/renesas-rpc-if.h |  8 +++-
 4 files changed, 75 insertions(+), 13 deletions(-)

diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 140cb4e2b789..7e20853df4a2 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
 
@@ -27,8 +28,8 @@
 #define RPCIF_CMNCR_MOIIO_HIZ	(RPCIF_CMNCR_MOIIO0(3) | \
 				 RPCIF_CMNCR_MOIIO1(3) | \
 				 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
-#define RPCIF_CMNCR_IO3FV(val)	(((val) & 0x3) << 14) /* undocumented */
-#define RPCIF_CMNCR_IO2FV(val)	(((val) & 0x3) << 12) /* undocumented */
+#define RPCIF_CMNCR_IO3FV(val)	(((val) & 0x3) << 14) /* documented for RZ/G2L */
+#define RPCIF_CMNCR_IO2FV(val)	(((val) & 0x3) << 12) /* documented for RZ/G2L */
 #define RPCIF_CMNCR_IO0FV(val)	(((val) & 0x3) << 8)
 #define RPCIF_CMNCR_IOFV_HIZ	(RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
 				 RPCIF_CMNCR_IO3FV(3))
@@ -126,6 +127,9 @@
 #define RPCIF_SMDRENR_OPDRE	BIT(4)
 #define RPCIF_SMDRENR_SPIDRE	BIT(0)
 
+#define RPCIF_PHYADD		0x0070	/* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
+#define RPCIF_PHYWR		0x0074	/* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
+
 #define RPCIF_PHYCNT		0x007C	/* R/W */
 #define RPCIF_PHYCNT_CAL	BIT(31)
 #define RPCIF_PHYCNT_OCTA(v)	(((v) & 0x3) << 22)
@@ -133,10 +137,12 @@
 #define RPCIF_PHYCNT_OCT	BIT(20)
 #define RPCIF_PHYCNT_DDRCAL	BIT(19)
 #define RPCIF_PHYCNT_HS		BIT(18)
-#define RPCIF_PHYCNT_STRTIM(v)	(((v) & 0x7) << 15)
+#define RPCIF_PHYCNT_CKSEL(v)	(((v) & 0x3) << 16) /* valid only for RZ/G2L */
+#define RPCIF_PHYCNT_STRTIM(v)	(((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
 #define RPCIF_PHYCNT_WBUF2	BIT(4)
 #define RPCIF_PHYCNT_WBUF	BIT(2)
 #define RPCIF_PHYCNT_PHYMEM(v)	(((v) & 0x3) << 0)
+#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
 
 #define RPCIF_PHYOFFSET1	0x0080	/* R/W */
 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
@@ -245,18 +251,46 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
 		return PTR_ERR(rpc->dirmap);
 	rpc->size = resource_size(res);
 
+	rpc->type = (enum rpcif_type)of_device_get_match_data(dev);
 	rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 
 	return PTR_ERR_OR_ZERO(rpc->rstc);
 }
 EXPORT_SYMBOL(rpcif_sw_init);
 
-void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
+static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
+{
+	u32 data;
+
+	regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
+	regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
+	regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
+	regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
+	regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
+	regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
+
+	regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
+	regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
+	regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
+	regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
+}
+
+int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 {
 	u32 dummy;
 
 	pm_runtime_get_sync(rpc->dev);
 
+	if (rpc->type == RPCIF_RZ_G2L) {
+		int ret;
+
+		ret = reset_control_reset(rpc->rstc);
+		if (ret)
+			return ret;
+		usleep_range(200, 300);
+		rpcif_rzg2l_timing_adjust_sdr(rpc);
+	}
+
 	/*
 	 * NOTE: The 0x260 are undocumented bits, but they must be set.
 	 *	 RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
@@ -265,8 +299,15 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 	 *	 On H3 ES1.x, the value should be 0, while on others,
 	 *	 the value should be 7.
 	 */
-	regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
-		     RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
+	if (rpc->type == RPCIF_RCAR_GEN3) {
+		regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
+			     RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
+	} else {
+		regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
+		dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
+		dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
+		regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
+	}
 
 	/*
 	 * NOTE: The 0x1511144 are undocumented bits, but they must be set
@@ -283,9 +324,17 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 		regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 				   RPCIF_PHYINT_WPVAL, 0);
 
-	regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
-		     RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
-		     RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
+	if (rpc->type == RPCIF_RCAR_GEN3)
+		regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
+			     RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
+			     RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
+	else
+		regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
+			     RPCIF_CMNCR_MOIIO3(1) | RPCIF_CMNCR_MOIIO2(1) |
+			     RPCIF_CMNCR_MOIIO1(1) | RPCIF_CMNCR_MOIIO0(1) |
+			     RPCIF_CMNCR_IO3FV(2) | RPCIF_CMNCR_IO2FV(2) |
+			     RPCIF_CMNCR_IO0FV(2) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
+
 	/* Set RCF after BSZ update */
 	regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 	/* Dummy read according to spec */
@@ -296,6 +345,8 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 	pm_runtime_put(rpc->dev);
 
 	rpc->bus_size = hyperflash ? 2 : 1;
+
+	return 0;
 }
 EXPORT_SYMBOL(rpcif_hw_init);
 
@@ -613,7 +664,8 @@ static int rpcif_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id rpcif_of_match[] = {
-	{ .compatible = "renesas,rcar-gen3-rpc-if", },
+	{ .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
+	{ .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
 	{},
 };
 MODULE_DEVICE_TABLE(of, rpcif_of_match);
diff --git a/drivers/mtd/hyperbus/rpc-if.c b/drivers/mtd/hyperbus/rpc-if.c
index 367b0d72bf62..40bca89268c3 100644
--- a/drivers/mtd/hyperbus/rpc-if.c
+++ b/drivers/mtd/hyperbus/rpc-if.c
@@ -132,7 +132,9 @@ static int rpcif_hb_probe(struct platform_device *pdev)
 
 	rpcif_enable_rpm(&hyperbus->rpc);
 
-	rpcif_hw_init(&hyperbus->rpc, true);
+	error = rpcif_hw_init(&hyperbus->rpc, true);
+	if (error)
+		return error;
 
 	hyperbus->hbdev.map.size = hyperbus->rpc.size;
 	hyperbus->hbdev.map.virt = hyperbus->rpc.dirmap;
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index 727d7cf0a6ad..651d92028306 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -156,7 +156,9 @@ static int rpcif_spi_probe(struct platform_device *pdev)
 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD;
 	ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
 
-	rpcif_hw_init(rpc, false);
+	error = rpcif_hw_init(rpc, false);
+	if (error)
+		return error;
 
 	error = spi_register_controller(ctlr);
 	if (error) {
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 77c694a19149..7c93f5177532 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -57,6 +57,11 @@ struct rpcif_op {
 	} data;
 };
 
+enum rpcif_type {
+	RPCIF_RCAR_GEN3,
+	RPCIF_RZ_G2L,
+};
+
 struct rpcif {
 	struct device *dev;
 	void __iomem *base;
@@ -64,6 +69,7 @@ struct rpcif {
 	struct regmap *regmap;
 	struct reset_control *rstc;
 	size_t size;
+	enum rpcif_type type;
 	enum rpcif_data_dir dir;
 	u8 bus_size;
 	void *buffer;
@@ -78,7 +84,7 @@ struct rpcif {
 };
 
 int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
-void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
+int rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
 		   size_t *len);
 int rpcif_manual_xfer(struct rpcif *rpc);
-- 
2.17.1



  parent reply	other threads:[~2022-01-31 12:19 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-31 12:18 [PATCH 5.10.y-cip 00/27] Add RPCIF, SCI{F1} support to Renesas RZ/G2L SoC Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 01/27] dt-bindings: pincfg-node: Add "output-impedance-ohms" property Lad Prabhakar
2022-08-13 13:45   ` Pavel Machek
2022-08-14 21:37     ` Prabhakar Mahadev Lad
2022-01-31 12:18 ` [PATCH 5.10.y-cip 02/27] pinctrl: pinconf-generic: Add support for "output-impedance-ohms" to be extracted from DT files Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 03/27] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add output-impedance-ohms property Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 04/27] pinctrl: renesas: rzg2l: Rename RZG2L_SINGLE_PIN_GET_PORT macro Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 05/27] pinctrl: renesas: rzg2l: Add helper functions to read/write pin config Lad Prabhakar
2022-02-01 11:05   ` Pavel Machek
2022-01-31 12:18 ` [PATCH 5.10.y-cip 06/27] pinctrl: renesas: rzg2l: Add support to get/set pin config for GPIO port pins Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 07/27] pinctrl: renesas: rzg2l: Rename PIN_CFG_* macros to match HW manual Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 08/27] pinctrl: renesas: rzg2l: Add support to get/set drive-strength and output-impedance-ohms Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 09/27] dt-bindings: memory: renesas,rpc-if: Miscellaneous improvements Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 10/27] dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044 Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 11/27] dt-bindings: memory: renesas,rpc-if: Add optional interrupts property Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 12/27] mtd: hyperbus: rpc-if: Check return value of rpcif_sw_init() Lad Prabhakar
2022-02-01  3:08   ` nobuhiro1.iwamatsu
2022-01-31 12:18 ` [PATCH 5.10.y-cip 13/27] memory: renesas-rpc-if: Return error in case devm_ioremap_resource() fails Lad Prabhakar
2022-02-01  3:10   ` nobuhiro1.iwamatsu
2022-01-31 12:18 ` [PATCH 5.10.y-cip 14/27] memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 15/27] memory: renesas-rpc-if: correct whitespace Lad Prabhakar
2022-01-31 12:18 ` Lad Prabhakar [this message]
2022-02-01 11:08   ` [PATCH 5.10.y-cip 16/27] memory: renesas-rpc-if: Add support for RZ/G2L Pavel Machek
2022-02-01 11:20   ` Pavel Machek
2022-01-31 12:18 ` [PATCH 5.10.y-cip 17/27] clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 18/27] arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller node Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 19/27] arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash Lad Prabhakar
2022-02-01 11:10   ` Pavel Machek
2022-01-31 12:18 ` [PATCH 5.10.y-cip 20/27] clk: renesas: r9a07g044: Add clock and reset entry for SCI1 Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 21/27] dt-bindings: serial: renesas,scif: Make resets as a required property Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 22/27] dt-bindings: serial: renesas,sci: Document RZ/G2L SoC Lad Prabhakar
2022-01-31 12:18 ` [PATCH 5.10.y-cip 23/27] serial: sh-sci: Add support to deassert/assert reset line Lad Prabhakar
2022-01-31 12:19 ` [PATCH 5.10.y-cip 24/27] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
2022-01-31 12:19 ` [PATCH 5.10.y-cip 25/27] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board Lad Prabhakar
2022-02-01 11:11   ` Pavel Machek
2022-01-31 12:19 ` [PATCH 5.10.y-cip 26/27] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Lad Prabhakar
2022-01-31 12:19 ` [PATCH 5.10.y-cip 27/27] arm64: dts: renesas: r9a07g044: Sort psci node Lad Prabhakar
2022-02-01 11:22 ` [PATCH 5.10.y-cip 00/27] Add RPCIF, SCI{F1} support to Renesas RZ/G2L SoC Pavel Machek
2022-02-01 18:58 ` Pavel Machek

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