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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH] clk: renesas: r9a07g044: Use shared array for resets
Date: Wed,  9 Feb 2022 20:34:11 +0000	[thread overview]
Message-ID: <20220209203411.22332-1-biju.das.jz@bp.renesas.com> (raw)

Instead of split resets in common and drp, but using a shared array,
we can still separate RZ/G2L and RZ/V2L by setting .num_resets to
the 'highest reset number + 1' for the specific SoC.

This patch uses shared array and sets .num_resets to the
'highest reset number + 1' for RZ/G2L and RZ/V2L SoC.

Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 119 +++++++++++++---------------
 1 file changed, 54 insertions(+), 65 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 8817d3838735..bdfabb992a20 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -299,67 +299,56 @@ static const struct {
 #endif
 };
 
-static const struct {
-	struct rzg2l_reset common[84];
-#ifdef CONFIG_CLK_R9A07G054
-	struct rzg2l_reset drp[1];
-#endif
-} rzg2l_resets = {
-	.common = {
-		DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
-		DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
-		DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
-		DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
-		DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
-		DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
-		DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
-		DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
-		DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
-		DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
-		DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
-		DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
-		DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
-		DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
-		DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
-		DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
-		DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
-		DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
-		DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
-		DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
-		DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
-		DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
-		DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
-		DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
-		DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
-		DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
-		DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
-		DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
-		DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
-		DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
-		DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
-		DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
-		DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
-		DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
-		DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
-		DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
-		DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
-		DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
-		DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
-		DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
-		DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
-		DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
-		DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
-		DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
-		DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
-		DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
-		DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
-		DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
-		DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
-	},
-#ifdef CONFIG_CLK_R9A07G054
-	.drp = {
-	},
-#endif
+static struct rzg2l_reset r9a07g044_resets[] = {
+	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
+	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
+	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
+	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
+	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+	DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
+	DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
+	DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+	DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
+	DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
+	DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
+	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
+	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
+	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
+	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
+	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
+	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
+	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
+	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
+	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
+	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
+	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
+	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
+	DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
+	DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
+	DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
+	DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
+	DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
+	DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
+	DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
+	DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
+	DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
+	DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
+	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
+	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
+	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+	DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
+	DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
+	DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
+	DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
+	DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
+	DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
+	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
+	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
+	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
+	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
+	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
+	DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
 };
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
@@ -385,8 +374,8 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 
 	/* Resets */
-	.resets = rzg2l_resets.common,
-	.num_resets = ARRAY_SIZE(rzg2l_resets.common),
+	.resets = r9a07g044_resets,
+	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
 };
 
 #ifdef CONFIG_CLK_R9A07G054
@@ -407,7 +396,7 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
 
 	/* Resets */
-	.resets = rzg2l_resets.common,
-	.num_resets = ARRAY_SIZE(rzg2l_resets.common) + ARRAY_SIZE(rzg2l_resets.drp),
+	.resets = r9a07g044_resets,
+	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
 };
 #endif
-- 
2.17.1


             reply	other threads:[~2022-02-09 20:34 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-09 20:34 Biju Das [this message]
2022-02-10 12:59 ` [PATCH] clk: renesas: r9a07g044: Use shared array for resets Geert Uytterhoeven

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