From: Tudor Ambarus <tudor.ambarus@microchip.com> To: <p.yadav@ti.com>, <michael@walle.cc>, <broonie@kernel.org> Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <nicolas.ferre@microchip.com>, <zhengxunli@mxic.com.tw>, <jaimeliao@mxic.com.tw>, Tudor Ambarus <tudor.ambarus@microchip.com> Subject: [PATCH 1/4] spi: spi-mem: Allow specifying the byte order in DTR mode Date: Fri, 18 Feb 2022 16:58:57 +0200 [thread overview] Message-ID: <20220218145900.1440045-2-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in DTR mode. The byte order of 16-bit words is swapped when read or written in Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) mode. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because this may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Fortunately there are controllers that can swap back the bytes at runtime, fixing the endiannesses. Provide a way for the upper layers to specify the byte order in DTR mode. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- include/linux/spi/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..e1878417420c 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_bswap16: whether the byte order of 16-bit words is swapped when + * read or written in DTR mode compared to STR mode. * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data @@ -119,6 +121,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_bswap16 : 1; enum spi_mem_data_dir dir; unsigned int nbytes; union { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Tudor Ambarus <tudor.ambarus@microchip.com> To: <p.yadav@ti.com>, <michael@walle.cc>, <broonie@kernel.org> Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <nicolas.ferre@microchip.com>, <zhengxunli@mxic.com.tw>, <jaimeliao@mxic.com.tw>, Tudor Ambarus <tudor.ambarus@microchip.com> Subject: [PATCH 1/4] spi: spi-mem: Allow specifying the byte order in DTR mode Date: Fri, 18 Feb 2022 16:58:57 +0200 [thread overview] Message-ID: <20220218145900.1440045-2-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in DTR mode. The byte order of 16-bit words is swapped when read or written in Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) mode. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because this may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Fortunately there are controllers that can swap back the bytes at runtime, fixing the endiannesses. Provide a way for the upper layers to specify the byte order in DTR mode. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- include/linux/spi/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..e1878417420c 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_bswap16: whether the byte order of 16-bit words is swapped when + * read or written in DTR mode compared to STR mode. * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data @@ -119,6 +121,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_bswap16 : 1; enum spi_mem_data_dir dir; unsigned int nbytes; union { -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-02-18 15:01 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-18 14:58 [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode Tudor Ambarus 2022-02-18 14:58 ` Tudor Ambarus 2022-02-18 14:58 ` Tudor Ambarus [this message] 2022-02-18 14:58 ` [PATCH 1/4] spi: " Tudor Ambarus 2022-03-02 10:02 ` Pratyush Yadav 2022-03-02 10:02 ` Pratyush Yadav 2022-03-10 5:31 ` Tudor.Ambarus 2022-03-10 5:31 ` Tudor.Ambarus 2022-03-11 17:47 ` Pratyush Yadav 2022-03-11 17:47 ` Pratyush Yadav 2022-02-18 14:58 ` [PATCH 2/4] mtd: spi-nor: core: " Tudor Ambarus 2022-02-18 14:58 ` Tudor Ambarus 2022-02-21 7:36 ` Michael Walle 2022-02-21 7:36 ` Michael Walle 2022-02-22 14:02 ` Tudor.Ambarus 2022-02-22 14:02 ` Tudor.Ambarus 2022-02-22 14:23 ` Michael Walle 2022-02-22 14:23 ` Michael Walle 2022-03-02 11:34 ` Pratyush Yadav 2022-03-02 11:34 ` Pratyush Yadav 2022-03-10 8:54 ` Tudor.Ambarus 2022-03-10 8:54 ` Tudor.Ambarus 2022-02-18 14:58 ` [PATCH 3/4] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Tudor Ambarus 2022-02-18 14:58 ` Tudor Ambarus 2022-02-21 7:40 ` Michael Walle 2022-02-21 7:40 ` Michael Walle 2022-03-02 12:28 ` Pratyush Yadav 2022-03-02 12:28 ` Pratyush Yadav 2022-02-18 14:59 ` [PATCH 4/4] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Tudor Ambarus 2022-02-18 14:59 ` Tudor Ambarus 2022-02-21 7:41 ` Michael Walle 2022-02-21 7:41 ` Michael Walle 2022-03-02 12:30 ` Pratyush Yadav 2022-03-02 12:30 ` Pratyush Yadav 2022-03-10 4:42 ` Tudor.Ambarus 2022-03-10 4:42 ` Tudor.Ambarus 2022-02-21 7:44 ` [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode Michael Walle 2022-02-21 7:44 ` Michael Walle 2022-02-22 13:54 ` Tudor.Ambarus 2022-02-22 13:54 ` Tudor.Ambarus 2022-02-22 14:13 ` Michael Walle 2022-02-22 14:13 ` Michael Walle 2022-02-22 14:23 ` Tudor.Ambarus 2022-02-22 14:23 ` Tudor.Ambarus 2022-02-22 14:27 ` Michael Walle 2022-02-22 14:27 ` Michael Walle 2022-02-22 14:43 ` Tudor.Ambarus 2022-02-22 14:43 ` Tudor.Ambarus 2022-02-23 18:38 ` Pratyush Yadav 2022-02-23 18:38 ` Pratyush Yadav 2022-02-24 6:08 ` Tudor.Ambarus 2022-02-24 6:08 ` Tudor.Ambarus 2022-02-24 6:37 ` Tudor.Ambarus 2022-02-24 6:37 ` Tudor.Ambarus 2022-02-24 9:37 ` Michael Walle 2022-02-24 9:37 ` Michael Walle 2022-02-24 10:27 ` Tudor.Ambarus 2022-02-24 10:27 ` Tudor.Ambarus 2022-02-25 7:35 ` zhengxunli 2022-02-25 7:35 ` zhengxunli 2022-02-24 13:24 ` Pratyush Yadav 2022-02-24 13:24 ` Pratyush Yadav 2022-02-24 14:02 ` Michael Walle 2022-02-24 14:02 ` Michael Walle 2022-02-24 14:33 ` Tudor.Ambarus 2022-02-24 14:33 ` Tudor.Ambarus
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