From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
To: <linux-clk@vger.kernel.org>
Cc: <git@xilinx.com>, <michal.simek@xilinx.com>,
<linux-kernel@vger.kernel.org>,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Subject: [PATCH 1/2] clk: zynq: trivial warning fix
Date: Tue, 22 Feb 2022 18:39:02 +0530 [thread overview]
Message-ID: <20220222130903.17235-2-shubhrajyoti.datta@xilinx.com> (raw)
In-Reply-To: <20220222130903.17235-1-shubhrajyoti.datta@xilinx.com>
Fix the below warning
WARNING: Missing a blank line after declarations
+ int enable = !!(fclk_enable & BIT(i - fclk0));
+ zynq_clk_register_fclk(i, clk_output_name[i],
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
drivers/clk/zynq/clkc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 204b83d911b9..434511dcf5cb 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np)
/* Peripheral clocks */
for (i = fclk0; i <= fclk3; i++) {
int enable = !!(fclk_enable & BIT(i - fclk0));
+
zynq_clk_register_fclk(i, clk_output_name[i],
SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
periph_parents, enable);
--
2.17.1
next prev parent reply other threads:[~2022-02-22 13:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 13:09 [PATCH 0/2] clk: zynq: trivial fixes Shubhrajyoti Datta
2022-02-22 13:09 ` Shubhrajyoti Datta [this message]
2022-03-12 2:26 ` [PATCH 1/2] clk: zynq: trivial warning fix Stephen Boyd
2022-02-22 13:09 ` [PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk Shubhrajyoti Datta
2022-03-12 2:26 ` Stephen Boyd
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