From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Tsukasa OI <research_trasio@irq.a4lg.com>, Anup Patel <anup@brainfault.org>, Heiko Stuebner <heiko@sntech.de>, Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v5 1/6] RISC-V: Correctly print supported extensions Date: Tue, 22 Feb 2022 12:48:06 -0800 [thread overview] Message-ID: <20220222204811.2281949-2-atishp@rivosinc.com> (raw) In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> From: Tsukasa OI <research_trasio@irq.a4lg.com> This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include <asm/smp.h> #include <asm/switch_to.h> +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Tsukasa OI <research_trasio@irq.a4lg.com>, Anup Patel <anup@brainfault.org>, Heiko Stuebner <heiko@sntech.de>, Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v5 1/6] RISC-V: Correctly print supported extensions Date: Tue, 22 Feb 2022 12:48:06 -0800 [thread overview] Message-ID: <20220222204811.2281949-2-atishp@rivosinc.com> (raw) In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> From: Tsukasa OI <research_trasio@irq.a4lg.com> This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include <asm/smp.h> #include <asm/switch_to.h> +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-02-22 20:48 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-22 20:48 [PATCH v5 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-22 20:48 ` Atish Patra [this message] 2022-02-22 20:48 ` [PATCH v5 1/6] RISC-V: Correctly print supported extensions Atish Patra 2022-02-22 20:48 ` [PATCH v5 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-28 10:03 ` Anup Patel 2022-02-28 10:03 ` Anup Patel 2022-02-22 20:48 ` [PATCH v5 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-28 10:03 ` Anup Patel 2022-02-28 10:03 ` Anup Patel 2022-02-22 20:48 ` [PATCH v5 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-28 10:06 ` Anup Patel 2022-02-28 10:06 ` Anup Patel 2022-02-22 20:48 ` [PATCH v5 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-28 10:06 ` Anup Patel 2022-02-28 10:06 ` Anup Patel 2022-02-22 20:48 ` [PATCH v5 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra 2022-02-22 20:48 ` Atish Patra 2022-02-23 1:13 ` kernel test robot 2022-02-28 10:07 ` Anup Patel 2022-02-28 10:07 ` Anup Patel 2022-03-10 23:50 ` [PATCH v5 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt 2022-03-10 23:50 ` Palmer Dabbelt 2022-03-11 0:21 ` Atish Kumar Patra 2022-03-11 0:21 ` Atish Kumar Patra 2022-03-11 12:42 ` Nick Kossifidis 2022-03-11 12:42 ` Nick Kossifidis 2022-03-11 13:10 ` Anup Patel 2022-03-11 13:10 ` Anup Patel
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