From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org>, dri-devel <dri-devel@lists.freedesktop.org> Cc: Hellstrom Thomas <thomas.hellstrom@intel.com>, Matthew Auld <matthew.auld@intel.com>, Chris Wilson <chris@chris-wilson.co.uk> Subject: [PATCH v3 1/6] drm/i915/gt: Use XY_FASR_COLOR_BLT to clear obj on graphics ver 12+ Date: Mon, 7 Mar 2022 19:10:33 +0530 [thread overview] Message-ID: <20220307134038.30525-2-ramalingam.c@intel.com> (raw) In-Reply-To: <20220307134038.30525-1-ramalingam.c@intel.com> XY_FAST_COLOR_BLT cmd is faster than the older XY_COLOR_BLT. Hence for clearing (Zero out) the pages of the newly allocated object, faster cmd is used. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 ++ drivers/gpu/drm/i915/gt/intel_migrate.c | 51 +++++++++++++++++--- 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index d112ffd56418..925e55b6a94f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -205,6 +205,11 @@ #define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2)) #define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22) +#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22) +#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19) +#define XY_FAST_COLOR_BLT_DW 16 +#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) +#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 20444d6ceb3c..cb68f7bf6b28 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -16,6 +16,8 @@ struct insert_pte_data { }; #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */ +#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \ + DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0) static bool engine_supports_migration(struct intel_engine_cs *engine) { @@ -614,20 +616,56 @@ intel_context_migrate_copy(struct intel_context *ce, return err; } -static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) +static int emit_clear(struct i915_request *rq, u64 offset, int size, + u32 value, bool is_lmem) { - const int ver = GRAPHICS_VER(rq->engine->i915); - u32 *cs; + struct drm_i915_private *i915 = rq->engine->i915; + int mocs = rq->engine->gt->mocs.uc_index << 1; + const int ver = GRAPHICS_VER(i915); + u32 *cs, mem_type = 0; + int ring_sz; GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX); offset += (u64)rq->engine->instance << 32; - cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6); + if (ver >= 12) + ring_sz = 16; + else if (ver >= 8) + ring_sz = 8; + else + ring_sz = 6; + + if (!is_lmem) + mem_type = 1 << XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT; + + cs = intel_ring_begin(rq, ring_sz); if (IS_ERR(cs)) return PTR_ERR(cs); - if (ver >= 8) { + if (ver >= 12) { + *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 | + (XY_FAST_COLOR_BLT_DW - 2); + *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | + (PAGE_SIZE - 1); + *cs++ = 0; + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4; + *cs++ = lower_32_bits(offset); + *cs++ = upper_32_bits(offset); + *cs++ = mem_type; + /* BG7 */ + *cs++ = value; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + /* BG11 */ + *cs++ = 0; + *cs++ = 0; + /* BG13 */ + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + } else if (ver >= 8) { *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2); *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE; *cs++ = 0; @@ -645,7 +683,6 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) *cs++ = lower_32_bits(offset); *cs++ = value; } - intel_ring_advance(rq, cs); return 0; } @@ -711,7 +748,7 @@ intel_context_migrate_clear(struct intel_context *ce, if (err) goto out_rq; - err = emit_clear(rq, offset, len, value); + err = emit_clear(rq, offset, len, value, is_lmem); /* Arbitration is re-enabled between requests. */ out_rq: -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org>, dri-devel <dri-devel@lists.freedesktop.org> Cc: Hellstrom Thomas <thomas.hellstrom@intel.com>, Matthew Auld <matthew.auld@intel.com>, Chris Wilson <chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v3 1/6] drm/i915/gt: Use XY_FASR_COLOR_BLT to clear obj on graphics ver 12+ Date: Mon, 7 Mar 2022 19:10:33 +0530 [thread overview] Message-ID: <20220307134038.30525-2-ramalingam.c@intel.com> (raw) In-Reply-To: <20220307134038.30525-1-ramalingam.c@intel.com> XY_FAST_COLOR_BLT cmd is faster than the older XY_COLOR_BLT. Hence for clearing (Zero out) the pages of the newly allocated object, faster cmd is used. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 ++ drivers/gpu/drm/i915/gt/intel_migrate.c | 51 +++++++++++++++++--- 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index d112ffd56418..925e55b6a94f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -205,6 +205,11 @@ #define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2)) #define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22) +#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22) +#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19) +#define XY_FAST_COLOR_BLT_DW 16 +#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) +#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 20444d6ceb3c..cb68f7bf6b28 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -16,6 +16,8 @@ struct insert_pte_data { }; #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */ +#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \ + DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0) static bool engine_supports_migration(struct intel_engine_cs *engine) { @@ -614,20 +616,56 @@ intel_context_migrate_copy(struct intel_context *ce, return err; } -static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) +static int emit_clear(struct i915_request *rq, u64 offset, int size, + u32 value, bool is_lmem) { - const int ver = GRAPHICS_VER(rq->engine->i915); - u32 *cs; + struct drm_i915_private *i915 = rq->engine->i915; + int mocs = rq->engine->gt->mocs.uc_index << 1; + const int ver = GRAPHICS_VER(i915); + u32 *cs, mem_type = 0; + int ring_sz; GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX); offset += (u64)rq->engine->instance << 32; - cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6); + if (ver >= 12) + ring_sz = 16; + else if (ver >= 8) + ring_sz = 8; + else + ring_sz = 6; + + if (!is_lmem) + mem_type = 1 << XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT; + + cs = intel_ring_begin(rq, ring_sz); if (IS_ERR(cs)) return PTR_ERR(cs); - if (ver >= 8) { + if (ver >= 12) { + *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 | + (XY_FAST_COLOR_BLT_DW - 2); + *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | + (PAGE_SIZE - 1); + *cs++ = 0; + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4; + *cs++ = lower_32_bits(offset); + *cs++ = upper_32_bits(offset); + *cs++ = mem_type; + /* BG7 */ + *cs++ = value; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + /* BG11 */ + *cs++ = 0; + *cs++ = 0; + /* BG13 */ + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + } else if (ver >= 8) { *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2); *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE; *cs++ = 0; @@ -645,7 +683,6 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) *cs++ = lower_32_bits(offset); *cs++ = value; } - intel_ring_advance(rq, cs); return 0; } @@ -711,7 +748,7 @@ intel_context_migrate_clear(struct intel_context *ce, if (err) goto out_rq; - err = emit_clear(rq, offset, len, value); + err = emit_clear(rq, offset, len, value, is_lmem); /* Arbitration is re-enabled between requests. */ out_rq: -- 2.20.1
next prev parent reply other threads:[~2022-03-07 13:40 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-07 13:40 [PATCH v3 0/6] drm/i915/ttm: Evict and restore of compressed object Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 13:40 ` Ramalingam C [this message] 2022-03-07 13:40 ` [Intel-gfx] [PATCH v3 1/6] drm/i915/gt: Use XY_FASR_COLOR_BLT to clear obj on graphics ver 12+ Ramalingam C 2022-03-07 14:29 ` Hellstrom, Thomas 2022-03-07 14:29 ` [Intel-gfx] " Hellstrom, Thomas 2022-03-07 13:40 ` [PATCH v3 2/6] drm/i915/gt: Clear compress metadata for Flat-ccs objects Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 14:32 ` Hellstrom, Thomas 2022-03-07 14:32 ` Hellstrom, Thomas 2022-03-07 13:40 ` [PATCH v3 3/6] drm/ttm: Add a parameter to add extra pages into ttm_tt Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 13:40 ` [PATCH v3 4/6] drm/i915/gem: Add extra pages in ttm_tt for ccs data Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 15:32 ` Matthew Auld 2022-03-07 15:32 ` [Intel-gfx] " Matthew Auld 2022-03-07 13:40 ` [PATCH v3 5/6] drm/i915/gt: Optimize the migration loop Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 13:40 ` [PATCH v3 6/6] drm/i915/migrate: Evict and restore the flatccs capable lmem obj Ramalingam C 2022-03-07 13:40 ` [Intel-gfx] " Ramalingam C 2022-03-07 14:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ttm: Evict and restore of compressed object Patchwork 2022-03-07 14:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-07 15:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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