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From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Cc: daniele.ceraolospurio@intel.com, lucas.demarchi@intel.com,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation
Date: Wed,  9 Mar 2022 10:47:03 +0530	[thread overview]
Message-ID: <20220309051708.22644-4-ramalingam.c@intel.com> (raw)
In-Reply-To: <20220309051708.22644-1-ramalingam.c@intel.com>

From: Chris Wilson <chris@chris-wilson.co.uk>

The lrc_isolation test uses two contexts in order to read from one
context while poisoning from a second. The test verifies that the
writes of the second context do not leak into the first context. This is
done by first recording the register state from context A, forcing a
preemption to context B, and only then switching back to context A to
re-read the register state to see if anything changed. The sequence is
important (and internally controlled by semaphores), but it does require
that context A is submitted *before* context B, as context B has higher
priority to force the preemption.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 998e561694be..b064e824053f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1416,8 +1416,10 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 	}
 
 	if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+		pr_err("%s(%s): wait for reference results timed out\n",
+		       __func__, engine->name);
 		i915_request_put(rq);
-		err = -ETIME;
+		err = -EIO;
 		goto err_ref1;
 	}
 	i915_request_put(rq);
@@ -1440,6 +1442,17 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 		goto err_result1;
 	}
 
+	/* Wait until we record the register state before allowing preemption */
+	if (wait_for_submit(engine, rq, HZ / 5)) {
+		pr_err("%s(%s): wait for submission timed out\n",
+		       __func__, engine->name);
+		i915_request_put(rq);
+		err = -EIO;
+		goto err_result1;
+	}
+	while (READ_ONCE(*sema.va) && !signal_pending(current))
+		usleep_range(100, 500);
+
 	err = poison_registers(B, engine, poison, relative, &sema);
 	if (err) {
 		WRITE_ONCE(*sema.va, -1);
@@ -1448,6 +1461,8 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 	}
 
 	if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+		pr_err("%s(%s): wait for results timed out\n",
+		       __func__, engine->name);
 		i915_request_put(rq);
 		err = -ETIME;
 		goto err_result1;
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>
Cc: lucas.demarchi@intel.com, Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation
Date: Wed,  9 Mar 2022 10:47:03 +0530	[thread overview]
Message-ID: <20220309051708.22644-4-ramalingam.c@intel.com> (raw)
In-Reply-To: <20220309051708.22644-1-ramalingam.c@intel.com>

From: Chris Wilson <chris@chris-wilson.co.uk>

The lrc_isolation test uses two contexts in order to read from one
context while poisoning from a second. The test verifies that the
writes of the second context do not leak into the first context. This is
done by first recording the register state from context A, forcing a
preemption to context B, and only then switching back to context A to
re-read the register state to see if anything changed. The sequence is
important (and internally controlled by semaphores), but it does require
that context A is submitted *before* context B, as context B has higher
priority to force the preemption.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 998e561694be..b064e824053f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1416,8 +1416,10 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 	}
 
 	if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+		pr_err("%s(%s): wait for reference results timed out\n",
+		       __func__, engine->name);
 		i915_request_put(rq);
-		err = -ETIME;
+		err = -EIO;
 		goto err_ref1;
 	}
 	i915_request_put(rq);
@@ -1440,6 +1442,17 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 		goto err_result1;
 	}
 
+	/* Wait until we record the register state before allowing preemption */
+	if (wait_for_submit(engine, rq, HZ / 5)) {
+		pr_err("%s(%s): wait for submission timed out\n",
+		       __func__, engine->name);
+		i915_request_put(rq);
+		err = -EIO;
+		goto err_result1;
+	}
+	while (READ_ONCE(*sema.va) && !signal_pending(current))
+		usleep_range(100, 500);
+
 	err = poison_registers(B, engine, poison, relative, &sema);
 	if (err) {
 		WRITE_ONCE(*sema.va, -1);
@@ -1448,6 +1461,8 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
 	}
 
 	if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+		pr_err("%s(%s): wait for results timed out\n",
+		       __func__, engine->name);
 		i915_request_put(rq);
 		err = -ETIME;
 		goto err_result1;
-- 
2.20.1


  parent reply	other threads:[~2022-03-09  5:17 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-09  5:17 [PATCH 0/8] Patches for selftest_lrc Ramalingam C
2022-03-09  5:17 ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 1/8] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 2/8] drm/i915/selftests: Exercise cross-process context isolation Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` Ramalingam C [this message]
2022-03-09  5:17   ` [Intel-gfx] [PATCH 3/8] drm/i915/selftests: Flush the submission for lrc_isolation Ramalingam C
2022-03-09  5:17 ` [PATCH 4/8] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 5/8] drm/i915/selftests: Check for incomplete LRI from the context image Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 6/8] drm/i915/selftest: Clear the output buffers before GPU writes Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 7/8] drm/i915/selftest: Always cancel semaphore on error Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:17 ` [PATCH 8/8] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing Ramalingam C
2022-03-09  5:17   ` [Intel-gfx] " Ramalingam C
2022-03-09  5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Patches for selftest_lrc Patchwork
2022-03-09  6:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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