[Intel-gfx] [PATCH] drm/i915/dmc: Add DMC_EVT_HTP and DMC_EVT_CTL programming

[Anusha Srivatsa <anusha.srivatsa@intel.com>]

We need add some checks around DMC reloading to
prevents the rare possibility of some adversary
writing to a random mmio register

BSpec: 49193

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 10 ++++++++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3dc859032bac..81cc4c658e3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -29,6 +29,8 @@
 #include "intel_vga.h"
 #include "vlv_sideband.h"
 
+#define DMC_EVT_HTP_CTL_MAX	8
+
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain)
 {
@@ -1101,6 +1103,26 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 		 enabled_dbuf_slices);
 }
 
+static void tgl_dmc_mmio_prog(struct drm_i915_private *dev_priv)
+{
+	struct intel_dmc *dmc = &dev_priv->dmc;
+	int i, id;
+
+	for (i = 0; i <= DMC_EVT_HTP_CTL_MAX; i++) {
+		intel_de_write(dev_priv, TGL_MAIN_DMC_EVT_CTL(i), DMC_EVT_CTL_VAL);
+		intel_de_write(dev_priv, TGL_MAIN_DMC_EVT_HTP(i), DMC_EVT_HTP_VAL);
+	}
+	/* Pipe DMC MMIOs */
+	for (id = 1; i <= DMC_FW_MAX; id++) {
+		for (i = 0; i <= DMC_EVT_HTP_CTL_MAX; i++) {
+			intel_de_write(dev_priv, PIPEDMC_EVT_CTL_OFFSET(dmc->dmc_info[id].start_mmioaddr, i),
+			DMC_EVT_CTL_VAL);
+			intel_de_write(dev_priv, PIPEDMC_EVT_HTP_OFFSET(dmc->dmc_info[id].start_mmioaddr, i),
+			DMC_EVT_HTP_VAL);
+		}
+	}
+}
+
 static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config = {};
@@ -1139,6 +1161,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	gen9_disable_dc_states(dev_priv);
+	tgl_dmc_mmio_prog(dev_priv);
 }
 
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d652f19ff9..7e3ef777c26d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5525,6 +5525,16 @@
 #define TGL_DMC_DEBUG3		_MMIO(0x101090)
 #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
 
+/* Main DMC EVT_HTP and EVT_CTL registers  */
+#define DMC_EVT_CTL_VAL		0x00030100
+#define DMC_EVT_HTP_VAL		0x00000000
+#define TGL_MAIN_DMC_EVT_HTP(n)	_MMIO(0x8F004 + (n) * 4)
+#define TGL_MAIN_DMC_EVT_CTL(n)	_MMIO(0x8F034 + (n) * 4)
+#define PIPEDMC_EVT_HTP_BASE	0x00004
+#define PIPEDMC_EVT_CTL_BASE	0x00034
+#define PIPEDMC_EVT_HTP_OFFSET(addr, i)		_MMIO(addr + PIPEDMC_EVT_HTP_BASE + (i * 4))
+#define PIPEDMC_EVT_CTL_OFFSET(addr, i)		_MMIO(addr + PIPEDMC_EVT_CTL_BASE + (i * 4))
+
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT		_MMIO(0x42060)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
-- 
2.25.1