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From: Palmer Dabbelt <palmer@rivosinc.com>
To: linux-sparse@vger.kernel.org, Kito Cheng <kito.cheng@gmail.com>,
	linux-riscv@lists.infradead.org, mkl@pengutronix.de,
	aurelien@aurel32.net,
	Linus Torvalds <torvalds@linux-foundation.org>
Cc: Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v1 5/6] RISC-V: Add the Zicsr extension
Date: Fri,  1 Apr 2022 22:00:40 -0700	[thread overview]
Message-ID: <20220402050041.21302-6-palmer@rivosinc.com> (raw)
In-Reply-To: <20220402050041.21302-1-palmer@rivosinc.com>

Recent versions of binutils default to an ISA spec version that doesn't
include Zicsr as part of I, so Linux has recently started passing this
in -march.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target-riscv.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target-riscv.c b/target-riscv.c
index 5076bbaf..afd6fafa 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -17,6 +17,7 @@
 #define RISCV_EMBD	(1 << 9)
 #define RISCV_FPU	(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
 #define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
+#define RISCV_ZICSR	(1 << 10)
 
 static unsigned int riscv_flags;
 
@@ -34,9 +35,10 @@ static void parse_march_riscv(const char *arg)
 	}, extensions[] = {
 		{ "m",		RISCV_MUL|RISCV_DIV },
 		{ "a",		RISCV_ATOMIC },
-		{ "f",		RISCV_FLOAT|RISCV_FDIV },
-		{ "d",		RISCV_DOUBLE|RISCV_FDIV },
+		{ "f",		RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
+		{ "d",		RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
 		{ "c",		RISCV_COMP },
+		{ "_zicsr",	RISCV_ZICSR },
 	};
 	int i;
 
@@ -128,6 +130,8 @@ static void predefine_riscv(const struct target *self)
 		predefine("__riscv_mul", 1, "1");
 	if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV))
 		predefine("__riscv_muldiv", 1, "1");
+	if (riscv_flags & RISCV_ZICSR)
+		predefine("__riscv_zicsr", 1, "1");
 
 	if (cmodel)
 		predefine_strong("__riscv_cmodel_%s", cmodel);
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@rivosinc.com>
To: linux-sparse@vger.kernel.org, Kito Cheng <kito.cheng@gmail.com>,
	linux-riscv@lists.infradead.org, mkl@pengutronix.de,
	aurelien@aurel32.net,
	Linus Torvalds <torvalds@linux-foundation.org>
Cc: Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v1 5/6] RISC-V: Add the Zicsr extension
Date: Fri,  1 Apr 2022 22:00:40 -0700	[thread overview]
Message-ID: <20220402050041.21302-6-palmer@rivosinc.com> (raw)
In-Reply-To: <20220402050041.21302-1-palmer@rivosinc.com>

Recent versions of binutils default to an ISA spec version that doesn't
include Zicsr as part of I, so Linux has recently started passing this
in -march.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target-riscv.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target-riscv.c b/target-riscv.c
index 5076bbaf..afd6fafa 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -17,6 +17,7 @@
 #define RISCV_EMBD	(1 << 9)
 #define RISCV_FPU	(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
 #define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
+#define RISCV_ZICSR	(1 << 10)
 
 static unsigned int riscv_flags;
 
@@ -34,9 +35,10 @@ static void parse_march_riscv(const char *arg)
 	}, extensions[] = {
 		{ "m",		RISCV_MUL|RISCV_DIV },
 		{ "a",		RISCV_ATOMIC },
-		{ "f",		RISCV_FLOAT|RISCV_FDIV },
-		{ "d",		RISCV_DOUBLE|RISCV_FDIV },
+		{ "f",		RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
+		{ "d",		RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
 		{ "c",		RISCV_COMP },
+		{ "_zicsr",	RISCV_ZICSR },
 	};
 	int i;
 
@@ -128,6 +130,8 @@ static void predefine_riscv(const struct target *self)
 		predefine("__riscv_mul", 1, "1");
 	if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV))
 		predefine("__riscv_muldiv", 1, "1");
+	if (riscv_flags & RISCV_ZICSR)
+		predefine("__riscv_zicsr", 1, "1");
 
 	if (cmodel)
 		predefine_strong("__riscv_cmodel_%s", cmodel);
-- 
2.34.1


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http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2022-04-02  5:04 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-02  5:00 [PATCH v1 0/6] RISC-V -march handling improvements Palmer Dabbelt
2022-04-02  5:00 ` Palmer Dabbelt
2022-04-02  5:00 ` [PATCH v1 1/6] RISC-V: Respect -Wsparse-error for -march errors Palmer Dabbelt
2022-04-02  5:00   ` Palmer Dabbelt
2022-05-21 21:46   ` Luc Van Oostenryck
2022-05-21 21:46     ` Luc Van Oostenryck
2022-04-02  5:00 ` [PATCH v1 2/6] RISC-V: Match GCC's semantics for multiple -march instances Palmer Dabbelt
2022-04-02  5:00   ` Palmer Dabbelt
2022-05-21 21:52   ` Luc Van Oostenryck
2022-05-21 21:52     ` Luc Van Oostenryck
2022-04-02  5:00 ` [PATCH v1 3/6] RISC-V: Remove the unimplemented ISA extensions Palmer Dabbelt
2022-04-02  5:00   ` Palmer Dabbelt
2022-05-21 22:05   ` Luc Van Oostenryck
2022-05-21 22:05     ` Luc Van Oostenryck
2022-04-02  5:00 ` [PATCH v1 4/6] RISC-V: Remove "g" from the extension list Palmer Dabbelt
2022-04-02  5:00   ` Palmer Dabbelt
2022-04-02  5:00 ` Palmer Dabbelt [this message]
2022-04-02  5:00   ` [PATCH v1 5/6] RISC-V: Add the Zicsr extension Palmer Dabbelt
2022-04-02  5:00 ` [PATCH v1 6/6] RISC-V: Add the Zifencei extension Palmer Dabbelt
2022-04-02  5:00   ` Palmer Dabbelt
2022-04-04 17:52 ` [PATCH v1 0/6] RISC-V -march handling improvements Marc Kleine-Budde
2022-04-04 17:52   ` Marc Kleine-Budde
2022-04-04 23:15   ` Palmer Dabbelt
2022-04-04 23:15     ` Palmer Dabbelt
2022-05-21 21:23 ` Luc Van Oostenryck
2022-05-21 21:23   ` Luc Van Oostenryck
2022-07-05 23:09   ` Palmer Dabbelt
2022-07-05 23:09     ` Palmer Dabbelt

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