From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 2/4] clk: renesas: r9a07g043: Add ethernet clock sources
Date: Sat, 2 Apr 2022 08:46:24 +0100 [thread overview]
Message-ID: <20220402074626.25624-3-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220402074626.25624-1-biju.das.jz@bp.renesas.com>
Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g043-cpg.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 0c574e153d4d..b9011bc7fe49 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -32,7 +32,10 @@ enum clk_ids {
CLK_PLL3_DIV2_4,
CLK_PLL3_DIV2_4_2,
CLK_PLL5,
+ CLK_PLL5_500,
+ CLK_PLL5_250,
CLK_PLL6,
+ CLK_PLL6_250,
CLK_P1_DIV2,
/* Module Clocks */
@@ -57,6 +60,9 @@ static const struct clk_div_table dtable_1_32[] = {
{0, 0},
};
+/* Mux clock tables */
+static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
+
static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -73,7 +79,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+ DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
+ DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+ DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
/* Core output clk */
DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -85,6 +94,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
+ DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
+ DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,
+ sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
--
2.17.1
next prev parent reply other threads:[~2022-04-02 7:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-02 7:46 [PATCH v2 0/4] Add GPIO,ETHERNET and SDHI Clock/Reset entries for RZ/G2UL Biju Das
2022-04-02 7:46 ` [PATCH v2 1/4] clk: renesas: r9a07g043: Add GPIO clock and reset entries Biju Das
2022-04-02 7:46 ` Biju Das [this message]
2022-04-02 7:46 ` [PATCH v2 3/4] clk: renesas: r9a07g043: Add GbEthernet clock/reset Biju Das
2022-04-02 7:46 ` [PATCH v2 4/4] clk: renesas: r9a07g043: Add SDHI clock and reset entries Biju Das
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