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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 4/7] arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
Date: Sat,  2 Apr 2022 09:13:25 +0100	[thread overview]
Message-ID: <20220402081328.26292-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220402081328.26292-1-biju.das.jz@bp.renesas.com>

Add Gigabit Ethernet{0,1} nodes to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
 * Added Rb tag from Geert
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index f60186240912..850081cdf6a0 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -365,6 +365,46 @@
 			status = "disabled";
 		};
 
+		eth0: ethernet@11c20000 {
+			compatible = "renesas,r9a07g043-gbeth",
+				     "renesas,rzg2l-gbeth";
+			reg = <0 0x11c20000 0 0x10000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mux", "fil", "arp_ns";
+			phy-mode = "rgmii";
+			clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
+				 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
+				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
+			clock-names = "axi", "chi", "refclk";
+			resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		eth1: ethernet@11c30000 {
+			compatible = "renesas,r9a07g043-gbeth",
+				     "renesas,rzg2l-gbeth";
+			reg = <0 0x11c30000 0 0x10000>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mux", "fil", "arp_ns";
+			phy-mode = "rgmii";
+			clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
+				 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
+				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
+			clock-names = "axi", "chi", "refclk";
+			resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		phyrst: usbphy-ctrl@11c40000 {
 			reg = <0 0x11c40000 0 0x10000>;
 			/* place holder */
-- 
2.17.1


  parent reply	other threads:[~2022-04-02  8:13 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-02  8:13 [PATCH v2 0/7] Enable Ethernet and SDHI on RZ/G2UL SMARC EVK Biju Das
2022-04-02  8:13 ` [PATCH v2 1/7] arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node Biju Das
2022-04-02  8:13 ` [PATCH v2 2/7] arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins Biju Das
2022-04-02  8:13 ` [PATCH v2 3/7] arm64: dts: renesas: r9a07g043: Add SDHI nodes Biju Das
2022-04-02  8:13 ` Biju Das [this message]
2022-04-02  8:13 ` [PATCH v2 5/7] arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform Biju Das
2022-04-12 10:47   ` Geert Uytterhoeven
2022-04-02  8:13 ` [PATCH v2 6/7] arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC " Biju Das
2022-04-02  8:13 ` [PATCH v2 7/7] arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet " Biju Das

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