From: Vinod Koul <vkoul@kernel.org> To: Rob Clark <robdclark@gmail.com> Cc: Jonathan Marek <jonathan@marek.ca>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Abhinav Kumar <quic_abhinavk@quicinc.com>, dri-devel@lists.freedesktop.org, Bjorn Andersson <bjorn.andersson@linaro.org>, Vinod Koul <vkoul@kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 06/14] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Mon, 4 Apr 2022 22:04:28 +0530 [thread overview] Message-ID: <20220404163436.956875-7-vkoul@kernel.org> (raw) In-Reply-To: <20220404163436.956875-1-vkoul@kernel.org> Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 3584f5ee6bb3..dc27579bb5f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -126,7 +129,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { - if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -511,6 +513,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) mode_sel = CTL_DEFAULT_GROUP_ID << 28; + if (cfg->dsc) + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc); + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); @@ -522,6 +527,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->dsc) { + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + } } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index ac1544474022..97f326dff0af 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid * @stream_sel: Stream selection for multi-stream interfaces + * @dsc: DSC BIT masks used */ struct dpu_hw_intf_cfg { enum dpu_intf intf; @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; int stream_sel; + unsigned int dsc; }; /** -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org> To: Rob Clark <robdclark@gmail.com> Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson <bjorn.andersson@linaro.org>, Vinod Koul <vkoul@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Jonathan Marek <jonathan@marek.ca>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Abhinav Kumar <quic_abhinavk@quicinc.com>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 06/14] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Mon, 4 Apr 2022 22:04:28 +0530 [thread overview] Message-ID: <20220404163436.956875-7-vkoul@kernel.org> (raw) In-Reply-To: <20220404163436.956875-1-vkoul@kernel.org> Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 3584f5ee6bb3..dc27579bb5f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -126,7 +129,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { - if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -511,6 +513,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features))) mode_sel = CTL_DEFAULT_GROUP_ID << 28; + if (cfg->dsc) + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc); + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); @@ -522,6 +527,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->dsc) { + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + } } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index ac1544474022..97f326dff0af 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid * @stream_sel: Stream selection for multi-stream interfaces + * @dsc: DSC BIT masks used */ struct dpu_hw_intf_cfg { enum dpu_intf intf; @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; int stream_sel; + unsigned int dsc; }; /** -- 2.34.1
next prev parent reply other threads:[~2022-04-04 16:35 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-04 16:34 [PATCH v6 00/14] drm/msm: Add Display Stream Compression Support Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 01/14] drm/msm/dsi: add support for dsc data Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 02/14] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 03/14] drm/msm/disp/dpu1: Add support for DSC Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 04/14] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 05/14] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` Vinod Koul [this message] 2022-04-04 16:34 ` [PATCH v6 06/14] drm/msm/disp/dpu1: Add DSC support in hw_ctl Vinod Koul 2022-04-04 16:34 ` [PATCH v6 07/14] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 08/14] drm/msm/dpu: don't use merge_3d if DSC merge topology is used Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 09/14] drm/msm: Add missing num_dspp field documentation Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 10/14] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 11/14] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 12/14] drm/msm/dsi: add mode valid callback for dsi_mgr Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-04 16:34 ` [PATCH v6 13/14] drm/msm: Update generated headers Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-05 13:57 ` Dmitry Baryshkov 2022-04-05 13:57 ` Dmitry Baryshkov 2022-04-04 16:34 ` [PATCH v6 14/14] drm/msm/dsi: Add support for DSC configuration Vinod Koul 2022-04-04 16:34 ` Vinod Koul 2022-04-05 13:58 ` Dmitry Baryshkov 2022-04-05 13:58 ` Dmitry Baryshkov 2022-04-05 19:12 ` kernel test robot 2022-04-05 19:12 ` kernel test robot 2022-04-05 23:42 ` Dmitry Baryshkov 2022-04-05 23:42 ` Dmitry Baryshkov 2022-04-06 6:44 ` Vinod Koul 2022-04-06 6:44 ` Vinod Koul
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