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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 6/6] clk: renesas: r9a07g043: Add WDT clock and reset entries
Date: Mon, 25 Apr 2022 10:52:44 +0100	[thread overview]
Message-ID: <20220425095244.156720-7-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220425095244.156720-1-biju.das.jz@bp.renesas.com>

Add WDT{0,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ac2b361efbb6..c7e5efc17965 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -135,6 +135,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
 				0x534, 1),
 	DEF_MOD("ostm2",	R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
 				0x534, 2),
+	DEF_MOD("wdt0_pclk",	R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
+				0x548, 0),
+	DEF_MOD("wdt0_clk",	R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
+				0x548, 1),
+	DEF_MOD("wdt2_pclk",	R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
+				0x548, 4),
+	DEF_MOD("wdt2_clk",	R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
+				0x548, 5),
 	DEF_MOD("sdhi0_imclk",	R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
 				0x554, 0),
 	DEF_MOD("sdhi0_imclk2",	R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
@@ -220,6 +228,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
 	DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
 	DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
 	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
+	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
+	DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
 	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
 	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
 	DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
-- 
2.25.1


  parent reply	other threads:[~2022-04-25  9:53 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-25  9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25  9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
2022-04-28 12:20   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
2022-04-28 12:19   ` Geert Uytterhoeven
2022-04-28 12:23     ` Biju Das
2022-04-25  9:52 ` Biju Das [this message]
2022-04-28 12:18   ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Geert Uytterhoeven

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