From: Brian Norris <briannorris@chromium.org> To: Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de> Cc: Robin Murphy <robin.murphy@arm.com>, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Guenter Roeck <linux@roeck-us.net>, Brian Norris <briannorris@chromium.org> Subject: [PATCH v3 2/3] soc: rockchip: power-domain: Replace dsb() with smb() Date: Mon, 25 Apr 2022 18:45:43 -0700 [thread overview] Message-ID: <20220426014545.628100-2-briannorris@chromium.org> (raw) In-Reply-To: <20220426014545.628100-1-briannorris@chromium.org> It's unclear if these are really needed at all, but seemingly their purpose is only as a write barrier. Use the general macro instead of the ARM-specific one. This driver is partially marked for COMPILE_TEST'ing, but it doesn't build under non-ARM architectures. Fix this up before *really* enabling it for COMPILE_TEST. Signed-off-by: Brian Norris <briannorris@chromium.org> --- Changes in v3: * New in v3 drivers/soc/rockchip/pm_domains.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 1b029e494274..cf16ff9b73b3 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -178,7 +178,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, regmap_update_bits(pmu->regmap, pmu->info->req_offset, pd_info->req_mask, idle ? -1U : 0); - dsb(sy); + wmb(); /* Wait util idle_ack = 1 */ target_ack = idle ? pd_info->ack_mask : 0; @@ -285,7 +285,7 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, regmap_update_bits(pmu->regmap, pmu->info->pwr_offset, pd->info->pwr_mask, on ? 0 : -1U); - dsb(sy); + wmb(); if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, is_on == on, 0, 10000)) { -- 2.36.0.rc2.479.g8af0fa9b8e-goog
WARNING: multiple messages have this Message-ID (diff)
From: Brian Norris <briannorris@chromium.org> To: Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de> Cc: Robin Murphy <robin.murphy@arm.com>, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Guenter Roeck <linux@roeck-us.net>, Brian Norris <briannorris@chromium.org> Subject: [PATCH v3 2/3] soc: rockchip: power-domain: Replace dsb() with smb() Date: Mon, 25 Apr 2022 18:45:43 -0700 [thread overview] Message-ID: <20220426014545.628100-2-briannorris@chromium.org> (raw) In-Reply-To: <20220426014545.628100-1-briannorris@chromium.org> It's unclear if these are really needed at all, but seemingly their purpose is only as a write barrier. Use the general macro instead of the ARM-specific one. This driver is partially marked for COMPILE_TEST'ing, but it doesn't build under non-ARM architectures. Fix this up before *really* enabling it for COMPILE_TEST. Signed-off-by: Brian Norris <briannorris@chromium.org> --- Changes in v3: * New in v3 drivers/soc/rockchip/pm_domains.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 1b029e494274..cf16ff9b73b3 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -178,7 +178,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, regmap_update_bits(pmu->regmap, pmu->info->req_offset, pd_info->req_mask, idle ? -1U : 0); - dsb(sy); + wmb(); /* Wait util idle_ack = 1 */ target_ack = idle ? pd_info->ack_mask : 0; @@ -285,7 +285,7 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, regmap_update_bits(pmu->regmap, pmu->info->pwr_offset, pd->info->pwr_mask, on ? 0 : -1U); - dsb(sy); + wmb(); if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, is_on == on, 0, 10000)) { -- 2.36.0.rc2.479.g8af0fa9b8e-goog _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2022-04-26 1:46 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-26 1:45 [PATCH v3 1/3] soc: rockchip: Clean up Kconfig whitespace Brian Norris 2022-04-26 1:45 ` Brian Norris 2022-04-26 1:45 ` Brian Norris [this message] 2022-04-26 1:45 ` [PATCH v3 2/3] soc: rockchip: power-domain: Replace dsb() with smb() Brian Norris 2022-04-26 20:14 ` Guenter Roeck 2022-04-26 20:14 ` Guenter Roeck 2022-04-26 23:55 ` Peter Geis 2022-04-26 23:55 ` Peter Geis 2022-04-27 0:25 ` Robin Murphy 2022-04-27 0:25 ` Robin Murphy 2022-04-27 21:47 ` Brian Norris 2022-04-27 21:47 ` Brian Norris 2022-04-26 1:45 ` [PATCH v3 3/3] soc: rockchip: Fix compile-testing SoC drivers Brian Norris 2022-04-26 1:45 ` Brian Norris 2022-04-26 20:14 ` Guenter Roeck 2022-04-26 20:14 ` Guenter Roeck 2022-04-26 20:13 ` [PATCH v3 1/3] soc: rockchip: Clean up Kconfig whitespace Guenter Roeck 2022-04-26 20:13 ` Guenter Roeck 2022-04-30 14:05 ` Heiko Stuebner 2022-04-30 14:05 ` Heiko Stuebner
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220426014545.628100-2-briannorris@chromium.org \ --to=briannorris@chromium.org \ --cc=arnd@arndb.de \ --cc=heiko@sntech.de \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-rockchip@lists.infradead.org \ --cc=linux@roeck-us.net \ --cc=robin.murphy@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.