From: Adam Ford <aford173@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: shawnguo@kernel.org, aford@beaconembedded.com,
Adam Ford <aford173@gmail.com>
Subject: [PATCH 2/2] arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
Date: Tue, 26 Apr 2022 15:51:44 -0500 [thread overview]
Message-ID: <20220426205144.476234-2-aford173@gmail.com> (raw)
In-Reply-To: <20220426205144.476234-1-aford173@gmail.com>
There is a header for a DB9 serial port, but any attempts to use
hardware handshaking fail. Enable RTS and CTS pin muxing and enable
handshaking in the uart node.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
index 0f40b43ac091..02f37dcda7ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
@@ -175,6 +175,7 @@ &uart3 {
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ uart-has-rtscts;
status = "okay";
};
@@ -258,6 +259,8 @@ pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
+ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
+ MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};
--
2.34.1
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next prev parent reply other threads:[~2022-04-26 20:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-26 20:51 [PATCH 1/2] arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3 Adam Ford
2022-04-26 20:51 ` Adam Ford [this message]
2022-05-05 3:53 ` Shawn Guo
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