From: Russ Weight <russell.h.weight@intel.com>
To: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
lee.jones@linaro.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: trix@redhat.com, marpagan@redhat.com, lgoncalv@redhat.com,
matthew.gerlach@linux.intel.com,
basheer.ahmed.muddebihal@intel.com, tianfei.zhang@intel.com,
Russ Weight <russell.h.weight@intel.com>
Subject: [PATCH v17 3/5] fpga: cardbmc-sec: expose flash update count
Date: Thu, 28 Apr 2022 16:37:30 -0700 [thread overview]
Message-ID: <20220428233732.189425-4-russell.h.weight@intel.com> (raw)
In-Reply-To: <20220428233732.189425-1-russell.h.weight@intel.com>
Extend the FPGA Card BMC Secure Update driver to provide a sysfs file to
expose the flash update count.
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
---
v17:
- Update the Date and KernelVersion for the ABI documentation to Jul 2022
and 5.19 respectively.
- Change "m10bmc" in symbol names to "cardbmc" to reflect the fact that the
future devices will not necessarily use the MAX10.
v16:
- No Change
v15:
- Updated the Dates and KernelVersions in the ABI documentation
v14:
- No change
v13:
- Updated ABI documentation date and kernel version
v12:
- Updated Date and KernelVersion fields in ABI documentation
v11:
- No change
v10:
- Changed the path expression in the sysfs documentation to
replace the n3000 reference with something more generic to
accomodate other devices that use the same driver.
v9:
- Rebased to 5.12-rc2 next
- Updated Date and KernelVersion in ABI documentation
v8:
- Previously patch 3/6, otherwise no change
v7:
- Updated Date and KernelVersion in ABI documentation
v6:
- Changed flash_count_show() parameter list to achieve
reverse-christmas tree format.
- Added WARN_ON() call for (FLASH_COUNT_SIZE / stride) to ensure
that the proper count is passed to regmap_bulk_read().
v5:
- Renamed sysfs node user_flash_count to flash_count and updated the
sysfs documentation accordingly.
v4:
- Moved the sysfs file for displaying the flash count from the
FPGA Security Manager class driver to here. The
m10bmc_user_flash_count() function is removed and the
functionality is moved into a user_flash_count_show()
function.
- Added ABI documentation for the new sysfs entry
v3:
- Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_
- Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update
driver"
- Removed wrapper functions (m10bmc_raw_*, m10bmc_sys_*). The
underlying functions are now called directly.
v2:
- Renamed get_qspi_flash_count() to m10bmc_user_flash_count()
- Minor code cleanup per review comments
- Added m10bmc_ prefix to functions in m10bmc_iops structure
---
.../sysfs-driver-intel-cardbmc-sec-update | 8 +++++
drivers/fpga/intel-cardbmc-sec-update.c | 36 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-cardbmc-sec-update b/Documentation/ABI/testing/sysfs-driver-intel-cardbmc-sec-update
index c032fbe59614..80279a3e36a5 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-cardbmc-sec-update
+++ b/Documentation/ABI/testing/sysfs-driver-intel-cardbmc-sec-update
@@ -27,3 +27,11 @@ Description: Read only. Returns the root entry hash for the BMC image
"hash not programmed". This file is only visible if the
underlying device supports it.
Format: "0x%x".
+
+What: /sys/bus/platform/drivers/intel-cardbmc-sec-update/.../security/flash_count
+Date: Jul 2022
+KernelVersion: 5.19
+Contact: Russ Weight <russell.h.weight@intel.com>
+Description: Read only. Returns number of times the secure update
+ staging area has been flashed.
+ Format: "%u".
diff --git a/drivers/fpga/intel-cardbmc-sec-update.c b/drivers/fpga/intel-cardbmc-sec-update.c
index ba3559f3335d..12c8ebdf4c14 100644
--- a/drivers/fpga/intel-cardbmc-sec-update.c
+++ b/drivers/fpga/intel-cardbmc-sec-update.c
@@ -84,7 +84,43 @@ DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
+#define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */
+
+static ssize_t flash_count_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct bmc_sec *sec = dev_get_drvdata(dev);
+ unsigned int stride, num_bits;
+ u8 *flash_buf;
+ int cnt, ret;
+
+ stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+ num_bits = FLASH_COUNT_SIZE * 8;
+
+ flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
+ if (!flash_buf)
+ return -ENOMEM;
+
+ WARN_ON(FLASH_COUNT_SIZE % stride);
+ ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
+ flash_buf, FLASH_COUNT_SIZE / stride);
+ if (ret) {
+ dev_err(sec->dev,
+ "failed to read flash count: %x cnt %x: %d\n",
+ STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
+ goto exit_free;
+ }
+ cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
+
+exit_free:
+ kfree(flash_buf);
+
+ return ret ? : sysfs_emit(buf, "%u\n", cnt);
+}
+static DEVICE_ATTR_RO(flash_count);
+
static struct attribute *bmc_security_attrs[] = {
+ &dev_attr_flash_count.attr,
&dev_attr_bmc_root_entry_hash.attr,
&dev_attr_sr_root_entry_hash.attr,
&dev_attr_pr_root_entry_hash.attr,
--
2.25.1
next prev parent reply other threads:[~2022-04-28 23:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 23:37 [PATCH v17 0/5] Intel FPGA Card BMC Secure Update Driver Russ Weight
2022-04-28 23:37 ` [PATCH v17 1/5] mfd: intel-m10-bmc: Rename n3000bmc-secure driver Russ Weight
2022-04-28 23:37 ` [PATCH v17 2/5] fpga: cardbmc-sec: create bmc secure update driver Russ Weight
2022-04-30 16:51 ` Xu Yilun
2022-05-03 23:47 ` Russ Weight
2022-04-28 23:37 ` Russ Weight [this message]
2022-04-28 23:37 ` [PATCH v17 4/5] fpga: cardbmc-sec: expose canceled keys in sysfs Russ Weight
2022-04-28 23:37 ` [PATCH v17 5/5] fpga: cardbmc-sec: add card BMC secure update functions Russ Weight
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