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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v3 9/9] clk: renesas: r9a07g044: Add DSI clock and reset entries
Date: Sat, 30 Apr 2022 12:41:56 +0100	[thread overview]
Message-ID: <20220430114156.6260-10-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220430114156.6260-1-biju.das.jz@bp.renesas.com>

Add DSI clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
V2->V3:
 * No Change
V1->V2:
 * No Change
RFC->V1:
 * Added Rb tag from Geert
---
 drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b5ddc5058670..57ec50659bb3 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -194,7 +194,7 @@ static const struct {
 };
 
 static const struct {
-	struct rzg2l_mod_clk common[65];
+	struct rzg2l_mod_clk common[71];
 #ifdef CONFIG_CLK_R9A07G054
 	struct rzg2l_mod_clk drp[0];
 #endif
@@ -254,6 +254,18 @@ static const struct {
 					0x558, 1),
 		DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
 					0x558, 2),
+		DEF_MOD("dsi_pll_clk",	R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
+					0x568, 0),
+		DEF_MOD("dsi_sys_clk",	R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
+					0x568, 1),
+		DEF_MOD("dsi_aclk",	R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
+					0x568, 2),
+		DEF_MOD("dsi_pclk",	R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
+					0x568, 3),
+		DEF_MOD("dsi_vclk",	R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
+					0x568, 4),
+		DEF_MOD("dsi_lpclk",	R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
+					0x568, 5),
 		DEF_COUPLED("lcdc_a",	R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
 					0x56c, 0),
 		DEF_COUPLED("lcdc_p",	R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
@@ -355,6 +367,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
 	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
 	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+	DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
+	DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
+	DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
 	DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
 	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
 	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
-- 
2.25.1


      parent reply	other threads:[~2022-04-30 11:42 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-30 11:41 [PATCH v3 0/9] Add RZ/G2L Display clock support Biju Das
2022-04-30 11:41 ` [PATCH v3 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
2022-04-30 11:41 ` [PATCH v3 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2022-04-30 11:41 ` [PATCH v3 3/9] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2022-05-02 11:55   ` Geert Uytterhoeven
2022-04-30 11:41 ` [PATCH v3 4/9] clk: renesas: r9a07g044: Add M1 clock support Biju Das
2022-04-30 11:41 ` [PATCH v3 5/9] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2022-04-30 11:41 ` [PATCH v3 6/9] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2022-04-30 11:41 ` [PATCH v3 7/9] clk: renesas: r9a07g044: Add M4 " Biju Das
2022-04-30 11:41 ` [PATCH v3 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2022-04-30 11:41 ` Biju Das [this message]

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