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From: Michael Walle <michael@walle.cc>
To: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>,
	Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>,
	soc@kernel.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	Tudor.Ambarus@microchip.com,
	Horatiu Vultur <horatiu.vultur@microchip.com>,
	Michael Walle <michael@walle.cc>
Subject: [PATCH v4 04/13] ARM: dts: lan966x: add all flexcom usart nodes
Date: Tue,  3 May 2022 00:41:18 +0200	[thread overview]
Message-ID: <20220502224127.2604333-5-michael@walle.cc> (raw)
In-Reply-To: <20220502224127.2604333-1-michael@walle.cc>

Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.

Keep the nodes disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index e9d6c16d04cf..ae3ac08cfc3b 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0040000 0x800>;
 			status = "disabled";
+
+			usart0: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx1: flexcom@e0044000 {
@@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0044000 0x800>;
 			status = "disabled";
+
+			usart1: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		trng: rng@e0048000 {
@@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0060000 0x800>;
 			status = "disabled";
+
+			usart2: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx3: flexcom@e0064000 {
@@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0070000 0x800>;
 			status = "disabled";
+
+			usart4: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		timer0: timer@e008c000 {
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc>
To: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>,
	Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>,
	soc@kernel.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	Tudor.Ambarus@microchip.com,
	Horatiu Vultur <horatiu.vultur@microchip.com>,
	Michael Walle <michael@walle.cc>
Subject: [PATCH v4 04/13] ARM: dts: lan966x: add all flexcom usart nodes
Date: Tue,  3 May 2022 00:41:18 +0200	[thread overview]
Message-ID: <20220502224127.2604333-5-michael@walle.cc> (raw)
In-Reply-To: <20220502224127.2604333-1-michael@walle.cc>

Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.

Keep the nodes disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index e9d6c16d04cf..ae3ac08cfc3b 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0040000 0x800>;
 			status = "disabled";
+
+			usart0: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx1: flexcom@e0044000 {
@@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0044000 0x800>;
 			status = "disabled";
+
+			usart1: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		trng: rng@e0048000 {
@@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0060000 0x800>;
 			status = "disabled";
+
+			usart2: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx3: flexcom@e0064000 {
@@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0070000 0x800>;
 			status = "disabled";
+
+			usart4: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		timer0: timer@e008c000 {
-- 
2.30.2


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  parent reply	other threads:[~2022-05-02 22:41 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-02 22:41 [PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Michael Walle
2022-05-02 22:41 ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 01/13] ARM: dts: lan966x: swap dma channels for crypto node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 02/13] ARM: dts: lan966x: add sgpio node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 03/13] ARM: dts: lan966x: add missing uart DMA channel Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` Michael Walle [this message]
2022-05-02 22:41   ` [PATCH v4 04/13] ARM: dts: lan966x: add all flexcom usart nodes Michael Walle
2022-05-02 22:41 ` [PATCH v4 05/13] ARM: dts: lan966x: add flexcom SPI nodes Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 06/13] ARM: dts: lan966x: add flexcom I2C nodes Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 07/13] ARM: dts: lan966x: add basic Kontron KSwitch D10 support Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-02 22:41 ` [PATCH v4 08/13] ARM: dts: lan966x: add hwmon node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:25   ` Claudiu.Beznea
2022-05-09  6:25     ` Claudiu.Beznea
2022-05-02 22:41 ` [PATCH v4 09/13] ARM: dts: lan966x: add MIIM nodes Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:26   ` Claudiu.Beznea
2022-05-09  6:26     ` Claudiu.Beznea
2022-05-02 22:41 ` [PATCH v4 10/13] ARM: dts: lan966x: add reset switch reset node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:26   ` Claudiu.Beznea
2022-05-09  6:26     ` Claudiu.Beznea
2022-05-02 22:41 ` [PATCH v4 11/13] ARM: dts: lan966x: add serdes node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:26   ` Claudiu.Beznea
2022-05-09  6:26     ` Claudiu.Beznea
2022-05-02 22:41 ` [PATCH v4 12/13] ARM: dts: lan966x: add switch node Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:27   ` Claudiu.Beznea
2022-05-09  6:27     ` Claudiu.Beznea
2022-05-02 22:41 ` [PATCH v4 13/13] ARM: dts: kswitch-d10: enable networking Michael Walle
2022-05-02 22:41   ` Michael Walle
2022-05-09  6:27   ` Claudiu.Beznea
2022-05-09  6:27     ` Claudiu.Beznea
2022-05-04 10:16 ` [PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support Horatiu Vultur
2022-05-04 10:16   ` Horatiu Vultur
2022-05-11  9:07 ` Michael Walle
2022-05-11  9:07   ` Michael Walle

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