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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier
Date: Tue,  3 May 2022 21:22:18 +0300	[thread overview]
Message-ID: <20220503182242.18797-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220503182242.18797-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.

To allow us to eventually get accurate numbers for all our
DPLL clock derived state we need to move the DPLL calculation
to hapen much earlier. To that end we hoist it up to the just
after the fastset checks. For now we just do the easy code
motion, and the actual back feeding of the final DPLL clock
into the state will come later.

A slight change here is that now .crtc_compute_clock()
can get called while the shared_dpll is still assigned.
But since .crtc_compute_clock() no longer assignes new
shared_dplls this is perfectly fine.

TODO: I'd actually like to do this before the fastset check
so that if the DPLL state should change we actually do the
modeset. Which I think is what the video aficionados want,
but it might not be what the fans of fastboot want. Not yet
sure how to reconcile those conflicting requirements...

v2: s/return/goto/ in error handling

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
 drivers/gpu/drm/i915/display/intel_dpll.c    | 3 ---
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0decf3d24237..5e50e0d56088 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4905,10 +4905,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		crtc_state->update_wm_post = true;
 
 	if (mode_changed) {
-		ret = intel_dpll_crtc_compute_clock(state, crtc);
-		if (ret)
-			return ret;
-
 		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
 		if (ret)
 			return ret;
@@ -7801,6 +7797,11 @@ static int intel_atomic_check(struct drm_device *dev,
 					    new_crtc_state, i) {
 		if (intel_crtc_needs_modeset(new_crtc_state)) {
 			any_ms = true;
+
+			ret = intel_dpll_crtc_compute_clock(state, crtc);
+			if (ret)
+				goto fail;
+
 			continue;
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c19fb075ee6e..7f0538ee2b51 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1449,9 +1449,6 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
-	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-		return 0;
-
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-- 
2.35.1


  parent reply	other threads:[~2022-05-03 18:22 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 18:22 [Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-05-03 18:22 ` [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-05-16 12:11   ` Jani Nikula
2022-05-03 18:22 ` Ville Syrjala [this message]
2022-05-16 12:12   ` [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-05-16 13:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() Ville Syrjala
2022-05-16 12:29   ` Jani Nikula
2022-05-16 12:29   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT() Ville Syrjala
2022-05-16 12:36   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/ Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs Ville Syrjala
2022-05-16 12:41   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock() Ville Syrjala
2022-05-04  2:53   ` kernel test robot
2022-05-04 12:33   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:43     ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params Ville Syrjala
2022-05-04 21:21   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:52     ` Jani Nikula
2022-05-16 12:50   ` [Intel-gfx] [PATCH " Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-05-25 10:53   ` Jani Nikula
2022-05-25 11:28     ` Ville Syrjälä
2022-05-03 18:22 ` [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier Ville Syrjala
2022-05-25 10:57   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout Ville Syrjala
2022-05-25 10:58   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-05-25 11:03   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock " Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-05-25 11:08   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-05-25 11:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-05-25 11:24   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL Ville Syrjala
2022-05-25 11:30   ` Jani Nikula
2022-05-25 18:16     ` Matt Roper
2022-05-03 18:22 ` [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always Ville Syrjala
2022-05-30 12:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 19:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes Patchwork
2022-05-04 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2) Patchwork
2022-05-04 15:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3) Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  1:52 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4) Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  3:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-05  9:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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