From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Yassine Oudjana <yassine.oudjana@gmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings
Date: Wed, 4 May 2022 16:25:51 +0400 [thread overview]
Message-ID: <20220504122601.335495-3-y.oudjana@protonmail.com> (raw)
In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add reset definitions for Mediatek MT6735 resets provided by
infracfg and pericfg.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
MAINTAINERS | 2 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e917039b9d8c..de15c3d50d2d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@nbd.name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..86448f946568
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RST_MT6735_INFRACFG_H
+
+#define EMI_REG_RST 0
+#define DRAMC0_AO_RST 1
+#define AP_CIRQ_EINT_RST 3
+#define APXGPT_RST 4
+#define SCPSYS_RST 5
+#define KP_RST 6
+#define PMIC_WRAP_RST 7
+#define CLDMA_AO_TOP_RST 8
+#define EMI_RST 16
+#define CCIF_RST 17
+#define DRAMC0_RST 18
+#define EMI_AO_REG_RST 19
+#define CCIF_AO_RST 20
+#define TRNG_RST 21
+#define SYS_CIRQ_RST 22
+#define GCE_RST 23
+#define MM_IOMMU_RST 24
+#define CCIF1_RST 25
+#define CLDMA_TOP_PD_RST 26
+#define CBIP_P2P_MFG 27
+#define CBIP_P2P_APMIXED 28
+#define CBIP_P2P_CKSYS 29
+#define CBIP_P2P_MIPI 30
+#define CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..6cdfaa7ddadf
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H
+#define _DT_BINDINGS_RST_MT6735_PERICFG_H
+
+#define UART0_SW_RST 0
+#define UART1_SW_RST 1
+#define UART2_SW_RST 2
+#define UART3_SW_RST 3
+#define UART4_SW_RST 4
+#define BTIF_SW_RST 6
+#define DISP_PWM_SW_RST 7
+#define PWM_SW_RST 8
+#define AUXADC_SW_RST 10
+#define DMA_SW_RST 11
+#define IRDA_SW_RST 12
+#define IRTX_SW_RST 13
+#define THERM_SW_RST 16
+#define MSDC2_SW_RST 17
+#define MSDC3_SW_RST 17
+#define MSDC0_SW_RST 19
+#define MSDC1_SW_RST 20
+#define I2C0_SW_RST 22
+#define I2C1_SW_RST 23
+#define I2C2_SW_RST 24
+#define I2C3_SW_RST 25
+#define USB_SW_RST 28
+
+#define SPI0_SW_RST 33
+
+#endif
--
2.36.0
WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Yassine Oudjana <yassine.oudjana@gmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings
Date: Wed, 4 May 2022 16:25:51 +0400 [thread overview]
Message-ID: <20220504122601.335495-3-y.oudjana@protonmail.com> (raw)
In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add reset definitions for Mediatek MT6735 resets provided by
infracfg and pericfg.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
MAINTAINERS | 2 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e917039b9d8c..de15c3d50d2d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@nbd.name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..86448f946568
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RST_MT6735_INFRACFG_H
+
+#define EMI_REG_RST 0
+#define DRAMC0_AO_RST 1
+#define AP_CIRQ_EINT_RST 3
+#define APXGPT_RST 4
+#define SCPSYS_RST 5
+#define KP_RST 6
+#define PMIC_WRAP_RST 7
+#define CLDMA_AO_TOP_RST 8
+#define EMI_RST 16
+#define CCIF_RST 17
+#define DRAMC0_RST 18
+#define EMI_AO_REG_RST 19
+#define CCIF_AO_RST 20
+#define TRNG_RST 21
+#define SYS_CIRQ_RST 22
+#define GCE_RST 23
+#define MM_IOMMU_RST 24
+#define CCIF1_RST 25
+#define CLDMA_TOP_PD_RST 26
+#define CBIP_P2P_MFG 27
+#define CBIP_P2P_APMIXED 28
+#define CBIP_P2P_CKSYS 29
+#define CBIP_P2P_MIPI 30
+#define CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..6cdfaa7ddadf
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H
+#define _DT_BINDINGS_RST_MT6735_PERICFG_H
+
+#define UART0_SW_RST 0
+#define UART1_SW_RST 1
+#define UART2_SW_RST 2
+#define UART3_SW_RST 3
+#define UART4_SW_RST 4
+#define BTIF_SW_RST 6
+#define DISP_PWM_SW_RST 7
+#define PWM_SW_RST 8
+#define AUXADC_SW_RST 10
+#define DMA_SW_RST 11
+#define IRDA_SW_RST 12
+#define IRTX_SW_RST 13
+#define THERM_SW_RST 16
+#define MSDC2_SW_RST 17
+#define MSDC3_SW_RST 17
+#define MSDC0_SW_RST 19
+#define MSDC1_SW_RST 20
+#define I2C0_SW_RST 22
+#define I2C1_SW_RST 23
+#define I2C2_SW_RST 24
+#define I2C3_SW_RST 25
+#define USB_SW_RST 28
+
+#define SPI0_SW_RST 33
+
+#endif
--
2.36.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Yassine Oudjana <y.oudjana@protonmail.com>,
Yassine Oudjana <yassine.oudjana@gmail.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
Miles Chen <miles.chen@mediatek.com>,
Sam Shih <sam.shih@mediatek.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings
Date: Wed, 4 May 2022 16:25:51 +0400 [thread overview]
Message-ID: <20220504122601.335495-3-y.oudjana@protonmail.com> (raw)
In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add reset definitions for Mediatek MT6735 resets provided by
infracfg and pericfg.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
MAINTAINERS | 2 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e917039b9d8c..de15c3d50d2d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@nbd.name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..86448f946568
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RST_MT6735_INFRACFG_H
+
+#define EMI_REG_RST 0
+#define DRAMC0_AO_RST 1
+#define AP_CIRQ_EINT_RST 3
+#define APXGPT_RST 4
+#define SCPSYS_RST 5
+#define KP_RST 6
+#define PMIC_WRAP_RST 7
+#define CLDMA_AO_TOP_RST 8
+#define EMI_RST 16
+#define CCIF_RST 17
+#define DRAMC0_RST 18
+#define EMI_AO_REG_RST 19
+#define CCIF_AO_RST 20
+#define TRNG_RST 21
+#define SYS_CIRQ_RST 22
+#define GCE_RST 23
+#define MM_IOMMU_RST 24
+#define CCIF1_RST 25
+#define CLDMA_TOP_PD_RST 26
+#define CBIP_P2P_MFG 27
+#define CBIP_P2P_APMIXED 28
+#define CBIP_P2P_CKSYS 29
+#define CBIP_P2P_MIPI 30
+#define CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..6cdfaa7ddadf
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H
+#define _DT_BINDINGS_RST_MT6735_PERICFG_H
+
+#define UART0_SW_RST 0
+#define UART1_SW_RST 1
+#define UART2_SW_RST 2
+#define UART3_SW_RST 3
+#define UART4_SW_RST 4
+#define BTIF_SW_RST 6
+#define DISP_PWM_SW_RST 7
+#define PWM_SW_RST 8
+#define AUXADC_SW_RST 10
+#define DMA_SW_RST 11
+#define IRDA_SW_RST 12
+#define IRTX_SW_RST 13
+#define THERM_SW_RST 16
+#define MSDC2_SW_RST 17
+#define MSDC3_SW_RST 17
+#define MSDC0_SW_RST 19
+#define MSDC1_SW_RST 20
+#define I2C0_SW_RST 22
+#define I2C1_SW_RST 23
+#define I2C2_SW_RST 24
+#define I2C3_SW_RST 25
+#define USB_SW_RST 28
+
+#define SPI0_SW_RST 33
+
+#endif
--
2.36.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-04 12:32 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 12:25 [PATCH 00/13] Mediatek MT6735 main clock and reset drivers Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:48 ` Rob Herring
2022-05-16 23:48 ` Rob Herring
2022-05-16 23:48 ` Rob Herring
2022-05-04 12:25 ` Yassine Oudjana [this message]
2022-05-04 12:25 ` [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-04 12:25 ` [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 12:25 ` [PATCH 04/13] clk: composite: Export clk_unregister_composite Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220504122601.335495-3-y.oudjana@protonmail.com \
--to=yassine.oudjana@gmail.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=bgolaszewski@baylibre.com \
--cc=chun-jie.chen@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=ikjn@chromium.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=miles.chen@mediatek.com \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sam.shih@mediatek.com \
--cc=sboyd@kernel.org \
--cc=tinghan.shen@mediatek.com \
--cc=weiyi.lu@mediatek.com \
--cc=wenst@chromium.org \
--cc=y.oudjana@protonmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.