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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <bp@alien8.de>, <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
	<Smita.KoralahalliChannabasappa@amd.com>,
	<muralidhara.mk@amd.com>, <naveenkrishna.chatradhi@amd.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH 15/18] EDAC/amd64: Add init_csrows() into pvt->ops
Date: Mon, 9 May 2022 14:55:31 +0000	[thread overview]
Message-ID: <20220509145534.44912-16-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com>

From: Muralidhara M K <muralidhara.mk@amd.com>

GPU Nodes will use a different method to enumerate the chip select
(struct dimm_info) values. A function pointer should be used rather
than introduce another branching condition.

Prepare for this by adding init_csrows() to pvt->ops and set it as
needed based on currently supported systems.

Use a "umc" prefix for modern systems, since these use Unified Memory
Controllers (UMCs).

Use a "dct" prefix for newly-defined legacy functions, since these
systems use DRAM Controllers (DCTs).

Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
[Rebased/reworked patch and reworded commit message]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 11 +++++------
 drivers/edac/amd64_edac.h |  1 +
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index f1346416e64d..5beeeb2fd6a8 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3357,7 +3357,7 @@ static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
 	return nr_pages;
 }
 
-static int init_csrows_df(struct mem_ctl_info *mci)
+static int umc_init_csrows(struct mem_ctl_info *mci)
 {
 	struct amd64_pvt *pvt = mci->pvt_info;
 	enum edac_type edac_mode = EDAC_NONE;
@@ -3405,7 +3405,7 @@ static int init_csrows_df(struct mem_ctl_info *mci)
  * Initialize the array of csrow attribute instances, based on the values
  * from pci config hardware registers.
  */
-static int init_csrows(struct mem_ctl_info *mci)
+static int dct_init_csrows(struct mem_ctl_info *mci)
 {
 	struct amd64_pvt *pvt = mci->pvt_info;
 	enum edac_type edac_mode = EDAC_NONE;
@@ -3415,9 +3415,6 @@ static int init_csrows(struct mem_ctl_info *mci)
 	int nr_pages = 0;
 	u32 val;
 
-	if (pvt->umc)
-		return init_csrows_df(mci);
-
 	amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
 
 	pvt->nbcfg = val;
@@ -3768,6 +3765,7 @@ static struct low_ops umc_ops = {
 	.ecc_enabled			= umc_ecc_enabled,
 	.determine_edac_cap		= umc_determine_edac_cap,
 	.determine_edac_ctl_cap		= umc_determine_edac_ctl_cap,
+	.init_csrows			= umc_init_csrows,
 	.setup_mci_misc_attrs		= setup_mci_misc_attrs,
 };
 
@@ -3784,6 +3782,7 @@ static struct low_ops dct_ops = {
 	.ecc_enabled			= dct_ecc_enabled,
 	.determine_edac_cap		= dct_determine_edac_cap,
 	.determine_edac_ctl_cap		= dct_determine_edac_ctl_cap,
+	.init_csrows			= dct_init_csrows,
 	.setup_mci_misc_attrs		= setup_mci_misc_attrs,
 };
 
@@ -4005,7 +4004,7 @@ static int init_one_instance(struct amd64_pvt *pvt)
 
 	pvt->ops->setup_mci_misc_attrs(mci);
 
-	if (init_csrows(mci))
+	if (pvt->ops->init_csrows(mci))
 		mci->edac_cap = EDAC_FLAG_NONE;
 
 	ret = -ENODEV;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 93de7dea516a..1b879c3cfb36 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -477,6 +477,7 @@ struct low_ops {
 	unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt);
 	void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt);
 	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
+	int  (*init_csrows)(struct mem_ctl_info *mci);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
-- 
2.25.1


  parent reply	other threads:[~2022-05-09 14:57 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09 14:55 [PATCH 00/18] AMD64 EDAC Cleanup and Refactor Yazen Ghannam
2022-05-09 14:55 ` [PATCH 01/18] EDAC/amd64: Don't set up EDAC PCI control on Family 17h+ Yazen Ghannam
2022-05-09 14:55 ` [PATCH 02/18] EDAC/amd64: Remove scrub rate control for Family 17h and later Yazen Ghannam
2022-05-11 10:26   ` Borislav Petkov
2022-05-12 14:19     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 03/18] EDAC/amd64: Remove PCI Function 6 Yazen Ghannam
2022-05-09 14:55 ` [PATCH 04/18] EDAC/amd64: Remove PCI Function 0 Yazen Ghannam
2022-05-11 10:34   ` Borislav Petkov
2022-05-12 14:34     ` Yazen Ghannam
2022-05-13  9:56       ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 05/18] EDAC/amd64: Merge struct amd64_family_type into struct amd64_pvt Yazen Ghannam
2022-05-13 15:21   ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 06/18] EDAC/amd64: Add prep_chip_selects() into pvt->ops Yazen Ghannam
2022-05-18  8:10   ` Borislav Petkov
2022-05-19 14:42     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 07/18] EDAC/amd64: Add read_base_mask() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 08/18] EDAC/amd64: Add determine_memory_type() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 09/18] EDAC/amd64: Add get_ecc_sym_sz() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 10/18] EDAC/amd64: Add read_mc_regs() " Yazen Ghannam
2022-05-18 11:02   ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 11/18] EDAC/amd64: Add ecc_enabled() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 12/18] EDAC/amd64: Add determine_edac_cap() " Yazen Ghannam
2022-06-20 16:21   ` Borislav Petkov
2022-06-22 16:10     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 13/18] EDAC/amd64: Add determine_edac_ctl_cap() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 14/18] EDAC/amd64: Add setup_mci_misc_attrs() " Yazen Ghannam
2022-05-09 14:55 ` Yazen Ghannam [this message]
2022-05-09 14:55 ` [PATCH 16/18] EDAC/amd64: Add dump_misc_regs() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 17/18] EDAC/amd64: Add get_cs_mode() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 18/18] EDAC/amd64: Add get_err_info() " Yazen Ghannam

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