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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <bp@alien8.de>, <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
	<Smita.KoralahalliChannabasappa@amd.com>,
	<muralidhara.mk@amd.com>, <naveenkrishna.chatradhi@amd.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH 18/18] EDAC/amd64: Add get_err_info() into pvt->ops
Date: Mon, 9 May 2022 14:55:34 +0000	[thread overview]
Message-ID: <20220509145534.44912-19-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com>

From: Muralidhara M K <muralidhara.mk@amd.com>

GPU Nodes will use a different method to determine the chip select
and channel of an error. A function pointer should be used rather
than introduce another branching condition.

Prepare for this by adding get_err_info() to pvt->ops. This function is
only called from the modern code path, so a legacy function is not
defined.

Use a "umc" prefix for modern systems, since these use Unified Memory
Controllers (UMCs).

Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
[Rebased/reworked patch and reworded commit message]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 15 ++++++++++-----
 drivers/edac/amd64_edac.h |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 248d1082736e..81d165bcd252 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3067,10 +3067,16 @@ static inline void decode_bus_error(int node_id, struct mce *m)
  * Currently, we can derive the channel number by looking at the 6th nibble in
  * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
  * number.
+ *
+ * csrow can be derived from the lower 3 bits of MCA_SYND value.
+ *
+ * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
+ * the MCA_SYND[ErrorInformation] field.
  */
-static int find_umc_channel(struct mce *m)
+static void umc_get_err_info(struct mce *m, struct err_info *err)
 {
-	return (m->ipid & GENMASK(31, 0)) >> 20;
+	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
+	err->csrow = m->synd & 0x7;
 }
 
 static void decode_umc_error(int node_id, struct mce *m)
@@ -3092,8 +3098,6 @@ static void decode_umc_error(int node_id, struct mce *m)
 	if (m->status & MCI_STATUS_DEFERRED)
 		ecc_type = 3;
 
-	err.channel = find_umc_channel(m);
-
 	if (!(m->status & MCI_STATUS_SYNDV)) {
 		err.err_code = ERR_SYND;
 		goto log_error;
@@ -3108,7 +3112,7 @@ static void decode_umc_error(int node_id, struct mce *m)
 			err.err_code = ERR_CHANNEL;
 	}
 
-	err.csrow = m->synd & 0x7;
+	pvt->ops->get_err_info(m, &err);
 
 	if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
 		err.err_code = ERR_NORM_ADDR;
@@ -3757,6 +3761,7 @@ static struct low_ops umc_ops = {
 	.init_csrows			= umc_init_csrows,
 	.dump_misc_regs			= umc_dump_misc_regs,
 	.get_cs_mode			= umc_get_cs_mode,
+	.get_err_info			= umc_get_err_info,
 	.setup_mci_misc_attrs		= setup_mci_misc_attrs,
 };
 
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 1f64c08ae0ce..d5a64b0639bb 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -480,6 +480,7 @@ struct low_ops {
 	int  (*init_csrows)(struct mem_ctl_info *mci);
 	void (*dump_misc_regs)(struct amd64_pvt *pvt);
 	int  (*get_cs_mode)(int dimm, u8 ctrl, struct amd64_pvt *pvt);
+	void (*get_err_info)(struct mce *m, struct err_info *err);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
-- 
2.25.1


      parent reply	other threads:[~2022-05-09 14:58 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09 14:55 [PATCH 00/18] AMD64 EDAC Cleanup and Refactor Yazen Ghannam
2022-05-09 14:55 ` [PATCH 01/18] EDAC/amd64: Don't set up EDAC PCI control on Family 17h+ Yazen Ghannam
2022-05-09 14:55 ` [PATCH 02/18] EDAC/amd64: Remove scrub rate control for Family 17h and later Yazen Ghannam
2022-05-11 10:26   ` Borislav Petkov
2022-05-12 14:19     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 03/18] EDAC/amd64: Remove PCI Function 6 Yazen Ghannam
2022-05-09 14:55 ` [PATCH 04/18] EDAC/amd64: Remove PCI Function 0 Yazen Ghannam
2022-05-11 10:34   ` Borislav Petkov
2022-05-12 14:34     ` Yazen Ghannam
2022-05-13  9:56       ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 05/18] EDAC/amd64: Merge struct amd64_family_type into struct amd64_pvt Yazen Ghannam
2022-05-13 15:21   ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 06/18] EDAC/amd64: Add prep_chip_selects() into pvt->ops Yazen Ghannam
2022-05-18  8:10   ` Borislav Petkov
2022-05-19 14:42     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 07/18] EDAC/amd64: Add read_base_mask() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 08/18] EDAC/amd64: Add determine_memory_type() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 09/18] EDAC/amd64: Add get_ecc_sym_sz() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 10/18] EDAC/amd64: Add read_mc_regs() " Yazen Ghannam
2022-05-18 11:02   ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 11/18] EDAC/amd64: Add ecc_enabled() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 12/18] EDAC/amd64: Add determine_edac_cap() " Yazen Ghannam
2022-06-20 16:21   ` Borislav Petkov
2022-06-22 16:10     ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 13/18] EDAC/amd64: Add determine_edac_ctl_cap() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 14/18] EDAC/amd64: Add setup_mci_misc_attrs() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 15/18] EDAC/amd64: Add init_csrows() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 16/18] EDAC/amd64: Add dump_misc_regs() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 17/18] EDAC/amd64: Add get_cs_mode() " Yazen Ghannam
2022-05-09 14:55 ` Yazen Ghannam [this message]

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