From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <bp@alien8.de>, <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
<Smita.KoralahalliChannabasappa@amd.com>,
<muralidhara.mk@amd.com>, <naveenkrishna.chatradhi@amd.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH 03/18] EDAC/amd64: Remove PCI Function 6
Date: Mon, 9 May 2022 14:55:19 +0000 [thread overview]
Message-ID: <20220509145534.44912-4-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com>
PCI Function 6 is used on Family 17h and later to access scrub
registers. With scrub access removed, this function has no other use.
Remove all Function 6 PCI IDs and related code.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
drivers/edac/amd64_edac.c | 22 +---------------------
drivers/edac/amd64_edac.h | 10 +---------
2 files changed, 2 insertions(+), 30 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 3ec7eb4ceb4e..b2f7c14a287c 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2911,7 +2911,6 @@ static struct amd64_family_type family_types[] = {
[F17_CPUS] = {
.ctl_name = "F17h",
.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2921,7 +2920,6 @@ static struct amd64_family_type family_types[] = {
[F17_M10H_CPUS] = {
.ctl_name = "F17h_M10h",
.f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2931,7 +2929,6 @@ static struct amd64_family_type family_types[] = {
[F17_M30H_CPUS] = {
.ctl_name = "F17h_M30h",
.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6,
.max_mcs = 8,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2941,7 +2938,6 @@ static struct amd64_family_type family_types[] = {
[F17_M60H_CPUS] = {
.ctl_name = "F17h_M60h",
.f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2951,7 +2947,6 @@ static struct amd64_family_type family_types[] = {
[F17_M70H_CPUS] = {
.ctl_name = "F17h_M70h",
.f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2961,7 +2956,6 @@ static struct amd64_family_type family_types[] = {
[F19_CPUS] = {
.ctl_name = "F19h",
.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_19H_DF_F6,
.max_mcs = 8,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2971,7 +2965,6 @@ static struct amd64_family_type family_types[] = {
[F19_M10H_CPUS] = {
.ctl_name = "F19h_M10h",
.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6,
.max_mcs = 12,
.flags.zn_regs_v2 = 1,
.ops = {
@@ -2982,7 +2975,6 @@ static struct amd64_family_type family_types[] = {
[F19_M50H_CPUS] = {
.ctl_name = "F19h_M50h",
.f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
- .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -3295,7 +3287,7 @@ static void decode_umc_error(int node_id, struct mce *m)
/*
* Use pvt->F3 which contains the F3 CPU PCI device to get the related
* F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
- * Reserve F0 and F6 on systems with a UMC.
+ * Reserve F0 on systems with a UMC.
*/
static int
reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
@@ -3307,21 +3299,11 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
return -ENODEV;
}
- pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
- if (!pvt->F6) {
- pci_dev_put(pvt->F0);
- pvt->F0 = NULL;
-
- edac_dbg(1, "F6 not found: device 0x%x\n", pci_id2);
- return -ENODEV;
- }
-
if (!pci_ctl_dev)
pci_ctl_dev = &pvt->F0->dev;
edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
- edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));
return 0;
}
@@ -3357,7 +3339,6 @@ static void free_mc_sibling_devs(struct amd64_pvt *pvt)
{
if (pvt->umc) {
pci_dev_put(pvt->F0);
- pci_dev_put(pvt->F6);
} else {
pci_dev_put(pvt->F1);
pci_dev_put(pvt->F2);
@@ -4080,7 +4061,6 @@ static int hw_info_get(struct amd64_pvt *pvt)
return -ENOMEM;
pci_id1 = fam_type->f0_id;
- pci_id2 = fam_type->f6_id;
} else {
pci_id1 = fam_type->f1_id;
pci_id2 = fam_type->f2_id;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 48f1d97e1274..2c7b49479aa9 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -115,21 +115,13 @@
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
-#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
-#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
-#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
-#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
-#define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
-#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
-#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670
/*
* Function 1 - Address Map
@@ -501,7 +493,7 @@ struct amd64_family_flags {
struct amd64_family_type {
const char *ctl_name;
- u16 f0_id, f1_id, f2_id, f6_id;
+ u16 f0_id, f1_id, f2_id;
/* Maximum number of memory controllers per die/node. */
u8 max_mcs;
struct amd64_family_flags flags;
--
2.25.1
next prev parent reply other threads:[~2022-05-09 14:56 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 14:55 [PATCH 00/18] AMD64 EDAC Cleanup and Refactor Yazen Ghannam
2022-05-09 14:55 ` [PATCH 01/18] EDAC/amd64: Don't set up EDAC PCI control on Family 17h+ Yazen Ghannam
2022-05-09 14:55 ` [PATCH 02/18] EDAC/amd64: Remove scrub rate control for Family 17h and later Yazen Ghannam
2022-05-11 10:26 ` Borislav Petkov
2022-05-12 14:19 ` Yazen Ghannam
2022-05-09 14:55 ` Yazen Ghannam [this message]
2022-05-09 14:55 ` [PATCH 04/18] EDAC/amd64: Remove PCI Function 0 Yazen Ghannam
2022-05-11 10:34 ` Borislav Petkov
2022-05-12 14:34 ` Yazen Ghannam
2022-05-13 9:56 ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 05/18] EDAC/amd64: Merge struct amd64_family_type into struct amd64_pvt Yazen Ghannam
2022-05-13 15:21 ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 06/18] EDAC/amd64: Add prep_chip_selects() into pvt->ops Yazen Ghannam
2022-05-18 8:10 ` Borislav Petkov
2022-05-19 14:42 ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 07/18] EDAC/amd64: Add read_base_mask() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 08/18] EDAC/amd64: Add determine_memory_type() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 09/18] EDAC/amd64: Add get_ecc_sym_sz() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 10/18] EDAC/amd64: Add read_mc_regs() " Yazen Ghannam
2022-05-18 11:02 ` Borislav Petkov
2022-05-09 14:55 ` [PATCH 11/18] EDAC/amd64: Add ecc_enabled() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 12/18] EDAC/amd64: Add determine_edac_cap() " Yazen Ghannam
2022-06-20 16:21 ` Borislav Petkov
2022-06-22 16:10 ` Yazen Ghannam
2022-05-09 14:55 ` [PATCH 13/18] EDAC/amd64: Add determine_edac_ctl_cap() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 14/18] EDAC/amd64: Add setup_mci_misc_attrs() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 15/18] EDAC/amd64: Add init_csrows() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 16/18] EDAC/amd64: Add dump_misc_regs() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 17/18] EDAC/amd64: Add get_cs_mode() " Yazen Ghannam
2022-05-09 14:55 ` [PATCH 18/18] EDAC/amd64: Add get_err_info() " Yazen Ghannam
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