From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 0/2] Add GPT and POEG clock and reset entries
Date: Tue, 10 May 2022 12:06:51 +0100 [thread overview]
Message-ID: <20220510110653.7326-1-biju.das.jz@bp.renesas.com> (raw)
This patch series aims to add GPT and POEG clock and reset entries to
RZ/G2L CPG driver.
Biju Das (2):
clk: renesas: r9a07g044: Add GPT clock and reset entry
clk: renesas: r9a07g044: Add POEG clock and reset entries
drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
--
2.25.1
next reply other threads:[~2022-05-10 11:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 11:06 Biju Das [this message]
2022-05-10 11:06 ` [PATCH 1/2] clk: renesas: r9a07g044: Add GPT clock and reset entry Biju Das
2022-05-19 9:44 ` Geert Uytterhoeven
2022-05-10 11:06 ` [PATCH 2/2] clk: renesas: r9a07g044: Add POEG clock and reset entries Biju Das
2022-05-19 9:47 ` Geert Uytterhoeven
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