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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Andi Shyti <andi@etezian.org>,
	Matthew Auld <matthew.auld@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH] drm/i915/gem: Flush TLBs for all the tiles
Date: Tue, 10 May 2022 22:33:59 +0200	[thread overview]
Message-ID: <20220510203359.92530-1-andi.shyti@linux.intel.com> (raw)

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..444b9f96ba77c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -217,10 +217,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			intel_wakeref_t w;
+
+			with_intel_runtime_pm_if_active(gt->uncore->rpm, w)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
-- 
2.36.0


WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Matthew Auld <matthew.auld@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH] drm/i915/gem: Flush TLBs for all the tiles
Date: Tue, 10 May 2022 22:33:59 +0200	[thread overview]
Message-ID: <20220510203359.92530-1-andi.shyti@linux.intel.com> (raw)

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..444b9f96ba77c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -217,10 +217,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			intel_wakeref_t w;
+
+			with_intel_runtime_pm_if_active(gt->uncore->rpm, w)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
-- 
2.36.0


             reply	other threads:[~2022-05-10 20:34 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 20:33 Andi Shyti [this message]
2022-05-10 20:33 ` [Intel-gfx] [PATCH] drm/i915/gem: Flush TLBs for all the tiles Andi Shyti
2022-05-10 22:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-05-11  4:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-11  7:23 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin

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