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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Andi Shyti <andi@etezian.org>,
	Matthew Auld <matthew.auld@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH v4 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
Date: Wed, 11 May 2022 03:11:20 +0200	[thread overview]
Message-ID: <20220511011121.114226-3-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20220511011121.114226-1-andi.shyti@linux.intel.com>

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..37d23e328bd0c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -13,6 +13,7 @@
 #include "i915_gem_mman.h"
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
 
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 				 struct sg_table *pages,
@@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			int tmp;
+
+			with_intel_gt_pm_if_awake(gt, tmp)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Matthew Auld <matthew.auld@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH v4 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
Date: Wed, 11 May 2022 03:11:20 +0200	[thread overview]
Message-ID: <20220511011121.114226-3-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20220511011121.114226-1-andi.shyti@linux.intel.com>

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..37d23e328bd0c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -13,6 +13,7 @@
 #include "i915_gem_mman.h"
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
 
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 				 struct sg_table *pages,
@@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			int tmp;
+
+			with_intel_gt_pm_if_awake(gt, tmp)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
-- 
2.36.1


  parent reply	other threads:[~2022-05-11  1:11 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11  1:11 [PATCH v4 0/3] Clear TLB caches in all tiles when object is removed Andi Shyti
2022-05-11  1:11 ` [Intel-gfx] " Andi Shyti
2022-05-11  1:11 ` [PATCH v4 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Andi Shyti
2022-05-11  1:11   ` [Intel-gfx] " Andi Shyti
2022-05-11  8:26   ` Tvrtko Ursulin
2022-05-11  1:11 ` Andi Shyti [this message]
2022-05-11  1:11   ` [Intel-gfx] [PATCH v4 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj Andi Shyti
2022-05-11  1:11 ` [PATCH v4 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Andi Shyti
2022-05-11  1:11   ` [Intel-gfx] " Andi Shyti
2022-05-11  2:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear TLB caches in all tiles when object is removed Patchwork
2022-05-11  2:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-11  2:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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