From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
like.xu.linux@gmail.com, vkuznets@redhat.com,
kan.liang@linux.intel.com, wei.w.wang@intel.com,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v12 00/16] Introduce Architectural LBR for vPMU
Date: Tue, 17 May 2022 11:40:44 -0400 [thread overview]
Message-ID: <20220517154100.29983-1-weijiang.yang@intel.com> (raw)
Intel CPU model-specific LBR(Legacy LBR) evolved into Architectural
LBR(Arch LBR[0]), it's the replacement of legacy LBR on new platforms.
The native support patches were merged into 5.9 kernel tree, and this
patch series is to enable Arch LBR in vPMU so that guest can benefit
from the merits of the feature.
The main advantages of Arch LBR are [1]:
- Faster context switching due to XSAVES support and faster reset of
LBR MSRs via the new DEPTH MSR
- Faster LBR read for a non-PEBS event due to XSAVES support, which
lowers the overhead of the NMI handler.
- Linux kernel can support the LBR features without knowing the model
number of the current CPU.
From end user's point of view, the usage of Arch LBR is the same as
the Legacy LBR that has been merged in the mainline.
Note, in this series, we impose one restriction for guest Arch LBR:
Guest can only set the same LBR record depth as host, this is due to
the special behavior of MSR_ARCH_LBR_DEPTH: 1) On write to the MSR,
it'll reset all Arch LBR recording MSRs to 0s. 2) XRSTORS resets all
record MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH.
Enforcing the restriction keeps the KVM enabling patch simple and
straightforward.
[0] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
[1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/
Qemu patch:
https://patchwork.ozlabs.org/project/qemu-devel/cover/20220215195258.29149-1-weijiang.yang@intel.com/
Previous version:
v11: https://lore.kernel.org/all/20220506033305.5135-1-weijiang.yang@intel.com/
Changes in v12:
1. Refactor KVM pmu helpers and fixed some commit messages. (Kan)
2. Use SMRAM to save/restore MSR_ARCH_LBR_CTL at SMM entry/exit. (Paolo)
3. Add Kan's reviewed-by in commit messages.
4. Rebased to queue:kvm/kvm.git
Like Xu (6):
perf/x86/intel: Fix the comment about guest LBR support on KVM
perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR
KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR
KVM: x86: Refine the matching and clearing logic for supported_xss
KVM: x86: Add XSAVE Support for Architectural LBR
Sean Christopherson (1):
KVM: x86: Report XSS as an MSR to be saved if there are supported
features
Yang Weijiang (9):
KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS
KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list
KVM: x86/pmu: Refactor code to support guest Arch LBR
KVM: x86/vmx: Check Arch LBR config when return perf capabilities
KVM: nVMX: Add necessary Arch LBR settings for nested VM
KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest
KVM: x86/vmx: Flip Arch LBREn bit on guest state change
KVM: x86: Add Arch LBR data MSR access interface
KVM: x86/cpuid: Advertise Arch LBR feature in CPUID
arch/x86/events/intel/core.c | 3 +-
arch/x86/events/intel/lbr.c | 6 +-
arch/x86/include/asm/kvm_host.h | 3 +
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/vmx.h | 4 +
arch/x86/kvm/cpuid.c | 49 +++++++++-
arch/x86/kvm/vmx/capabilities.h | 9 ++
arch/x86/kvm/vmx/nested.c | 7 +-
arch/x86/kvm/vmx/pmu_intel.c | 159 +++++++++++++++++++++++++++----
arch/x86/kvm/vmx/vmcs12.c | 1 +
arch/x86/kvm/vmx/vmcs12.h | 3 +-
arch/x86/kvm/vmx/vmx.c | 80 +++++++++++++++-
arch/x86/kvm/x86.c | 23 ++++-
13 files changed, 310 insertions(+), 38 deletions(-)
base-commit: a3808d88461270c71d3fece5e51cc486ecdac7d0
--
2.27.0
next reply other threads:[~2022-05-17 15:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 15:40 Yang Weijiang [this message]
2022-05-17 15:40 ` [PATCH v12 01/16] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 02/16] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 03/16] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 04/16] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 05/16] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 06/16] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 07/16] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 08/16] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 09/16] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 10/16] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 11/16] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 12/16] KVM: nVMX: Add necessary Arch LBR settings for nested VM Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 13/16] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 14/16] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2022-05-17 15:40 ` [PATCH v12 15/16] KVM: x86: Add Arch LBR data MSR access interface Yang Weijiang
2022-05-17 15:41 ` [PATCH v12 16/16] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Yang Weijiang
2022-05-20 12:28 ` [PATCH v12 00/16] Introduce Architectural LBR for vPMU Paolo Bonzini
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