From: Po-Kai Chi <po-kai.chi@sifive.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Po-Kai Chi <po-kai.chi@sifive.com> Subject: [PATCH] riscv: Invalid instruction cache after copy the xol area Date: Wed, 18 May 2022 16:17:53 +0800 [thread overview] Message-ID: <20220518081753.29589-1-po-kai.chi@sifive.com> (raw) We need to invalid the relevant instruction cache after copying the xol area, to ensure the changes takes effect. Signed-off-by: Po-Kai Chi <po-kai.chi@sifive.com> --- arch/riscv/kernel/probes/uprobes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..9d52beeac73c 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -165,6 +165,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, /* Initialize the slot */ void *kaddr = kmap_atomic(page); void *dst = kaddr + (vaddr & ~PAGE_MASK); + unsigned long addr = (unsigned long)dst; memcpy(dst, src, len); @@ -177,10 +178,9 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, kunmap_atomic(kaddr); /* - * We probably need flush_icache_user_page() but it needs vma. - * This should work on most of architectures by default. If - * architecture needs to do something different it can define - * its own version of the function. + * Flush both I/D cache to ensure instruction modification + * takes effect. */ flush_dcache_page(page); + flush_icache_range(addr, addr + len); } -- 2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: Po-Kai Chi <po-kai.chi@sifive.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Po-Kai Chi <po-kai.chi@sifive.com> Subject: [PATCH] riscv: Invalid instruction cache after copy the xol area Date: Wed, 18 May 2022 16:17:53 +0800 [thread overview] Message-ID: <20220518081753.29589-1-po-kai.chi@sifive.com> (raw) We need to invalid the relevant instruction cache after copying the xol area, to ensure the changes takes effect. Signed-off-by: Po-Kai Chi <po-kai.chi@sifive.com> --- arch/riscv/kernel/probes/uprobes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..9d52beeac73c 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -165,6 +165,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, /* Initialize the slot */ void *kaddr = kmap_atomic(page); void *dst = kaddr + (vaddr & ~PAGE_MASK); + unsigned long addr = (unsigned long)dst; memcpy(dst, src, len); @@ -177,10 +178,9 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, kunmap_atomic(kaddr); /* - * We probably need flush_icache_user_page() but it needs vma. - * This should work on most of architectures by default. If - * architecture needs to do something different it can define - * its own version of the function. + * Flush both I/D cache to ensure instruction modification + * takes effect. */ flush_dcache_page(page); + flush_icache_range(addr, addr + len); } -- 2.36.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-05-18 8:18 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-18 8:17 Po-Kai Chi [this message] 2022-05-18 8:17 ` [PATCH] riscv: Invalid instruction cache after copy the xol area Po-Kai Chi 2022-06-16 22:04 ` Palmer Dabbelt 2022-06-16 22:04 ` Palmer Dabbelt 2022-07-06 7:28 ` Po-Kai Chi 2022-07-06 7:28 ` Po-Kai Chi 2022-05-19 3:23 kernel test robot 2023-11-30 2:03 Zong Li 2023-11-30 2:03 ` Zong Li
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