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From: Jonathan Liu <net147@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: Marek Vasut <marex@denx.de>, Maxime Ripard <maxime@cerno.tech>,
	Jonathan Liu <net147@gmail.com>,
	Jagan Teki <jagan@amarulasolutions.com>,
	Andrzej Hajda <andrzej.hajda@intel.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	linux-kernel@vger.kernel.org
Subject: [PATCH] drm: bridge: icn6211: Adjust clock phase using SYS_CTRL_1
Date: Mon, 23 May 2022 12:38:00 +1000	[thread overview]
Message-ID: <20220523023801.410050-1-net147@gmail.com> (raw)

The code from [1] sets SYS_CTRL_1 to different values depending on the
desired clock phase (0, 1/4, 1/2 or 3/4). A clock phase of 0 aligns the
positive edge of the clock with the pixel data while other values delay
the clock by a fraction of the clock period. A clock phase of 1/2 aligns
the negative edge of the clock with the pixel data.

The driver currently hard codes SYS_CTRL_1 to 0x88 which corresponds to
aligning the positive edge of the clock with the pixel data. This won't
work correctly for panels that require aligning the negative edge of the
clock with the pixel data.

Adjust the clock phase to 0 if DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE is
present in bus_flags, otherwise adjust the clock phase to 1/2 as
appropriate for DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE.

[1] https://github.com/tdjastrzebski/ICN6211-Configurator

Signed-off-by: Jonathan Liu <net147@gmail.com>
---
 drivers/gpu/drm/bridge/chipone-icn6211.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
index 47dea657a752..df0290059aa3 100644
--- a/drivers/gpu/drm/bridge/chipone-icn6211.c
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -57,6 +57,10 @@
 #define BIST_CHESS_XY_H		0x30
 #define BIST_FRAME_TIME_L	0x31
 #define BIST_FRAME_TIME_H	0x32
+#define CLK_PHASE_0		0x88
+#define CLK_PHASE_1_4		0x98
+#define CLK_PHASE_1_2		0xa8
+#define CLK_PHASE_3_4		0xb8
 #define FIFO_MAX_ADDR_LOW	0x33
 #define SYNC_EVENT_DLY		0x34
 #define HSW_MIN			0x35
@@ -414,7 +418,11 @@ static void chipone_atomic_enable(struct drm_bridge *bridge,
 	chipone_configure_pll(icn, mode);
 
 	chipone_writeb(icn, SYS_CTRL(0), 0x40);
-	chipone_writeb(icn, SYS_CTRL(1), 0x88);
+
+	if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
+		chipone_writeb(icn, SYS_CTRL(1), CLK_PHASE_0);
+	else
+		chipone_writeb(icn, SYS_CTRL(1), CLK_PHASE_1_2);
 
 	/* icn6211 specific sequence */
 	chipone_writeb(icn, MIPI_FORCE_0, 0x20);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Liu <net147@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: Marek Vasut <marex@denx.de>, Jonathan Liu <net147@gmail.com>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	David Airlie <airlied@linux.ie>, Jonas Karlman <jonas@kwiboo.se>,
	linux-kernel@vger.kernel.org,
	Robert Foss <robert.foss@linaro.org>,
	Maxime Ripard <maxime@cerno.tech>,
	Andrzej Hajda <andrzej.hajda@intel.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH] drm: bridge: icn6211: Adjust clock phase using SYS_CTRL_1
Date: Mon, 23 May 2022 12:38:00 +1000	[thread overview]
Message-ID: <20220523023801.410050-1-net147@gmail.com> (raw)

The code from [1] sets SYS_CTRL_1 to different values depending on the
desired clock phase (0, 1/4, 1/2 or 3/4). A clock phase of 0 aligns the
positive edge of the clock with the pixel data while other values delay
the clock by a fraction of the clock period. A clock phase of 1/2 aligns
the negative edge of the clock with the pixel data.

The driver currently hard codes SYS_CTRL_1 to 0x88 which corresponds to
aligning the positive edge of the clock with the pixel data. This won't
work correctly for panels that require aligning the negative edge of the
clock with the pixel data.

Adjust the clock phase to 0 if DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE is
present in bus_flags, otherwise adjust the clock phase to 1/2 as
appropriate for DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE.

[1] https://github.com/tdjastrzebski/ICN6211-Configurator

Signed-off-by: Jonathan Liu <net147@gmail.com>
---
 drivers/gpu/drm/bridge/chipone-icn6211.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
index 47dea657a752..df0290059aa3 100644
--- a/drivers/gpu/drm/bridge/chipone-icn6211.c
+++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
@@ -57,6 +57,10 @@
 #define BIST_CHESS_XY_H		0x30
 #define BIST_FRAME_TIME_L	0x31
 #define BIST_FRAME_TIME_H	0x32
+#define CLK_PHASE_0		0x88
+#define CLK_PHASE_1_4		0x98
+#define CLK_PHASE_1_2		0xa8
+#define CLK_PHASE_3_4		0xb8
 #define FIFO_MAX_ADDR_LOW	0x33
 #define SYNC_EVENT_DLY		0x34
 #define HSW_MIN			0x35
@@ -414,7 +418,11 @@ static void chipone_atomic_enable(struct drm_bridge *bridge,
 	chipone_configure_pll(icn, mode);
 
 	chipone_writeb(icn, SYS_CTRL(0), 0x40);
-	chipone_writeb(icn, SYS_CTRL(1), 0x88);
+
+	if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
+		chipone_writeb(icn, SYS_CTRL(1), CLK_PHASE_0);
+	else
+		chipone_writeb(icn, SYS_CTRL(1), CLK_PHASE_1_2);
 
 	/* icn6211 specific sequence */
 	chipone_writeb(icn, MIPI_FORCE_0, 0x20);
-- 
2.36.1


             reply	other threads:[~2022-05-23  2:38 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-23  2:38 Jonathan Liu [this message]
2022-05-23  2:38 ` [PATCH] drm: bridge: icn6211: Adjust clock phase using SYS_CTRL_1 Jonathan Liu
2022-05-23 11:10 ` Marek Vasut
2022-05-23 11:10   ` Marek Vasut

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