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From: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Chao-ying Fu <cfu@wavecomp.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Greg Ungerer <gerg@kernel.org>, Hauke Mehrtens <hauke@hauke-m.de>,
	Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	Marc Zyngier <maz@kernel.org>,
	Paul Burton <paulburton@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Serge Semin <fancer.lancer@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Tiezhu Yang <yangtiezhu@loongson.cn>,
	Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Subject: [PATCH v2 09/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core
Date: Wed, 25 May 2022 14:10:27 +0200	[thread overview]
Message-ID: <20220525121030.16054-10-Dragan.Mladjenovic@syrmia.com> (raw)
In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com>

From: Paul Burton <paulburton@kernel.org>

The pm-cps code has up until now used per-CPU variables indexed by core,
rather than CPU number, in order to share data amongst sibling CPUs (ie.
VPs/threads in a core). This works fine for single cluster systems, but
with multi-cluster systems a core number is no longer unique in the
system, leading to sharing between CPUs that are not actually siblings.

Avoid this issue by using per-CPU variables as they are more generally
used - ie. access them using CPU numbers rather than core numbers.
Sharing between siblings is then accomplished by:
 - Assigning the same pointer to entries for each sibling CPU for the
   nc_asm_enter & ready_count variables, which allow this by virtue of
   being per-CPU pointers.

 - Indexing by the first CPU set in a CPUs cpu_sibling_map in the case
   of pm_barrier, for which we can't use the previous approach because
   the per-CPU variable is not a pointer.

Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 9bf60d7d44d3..a7bcf2b814c8 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -56,10 +56,7 @@ static DEFINE_PER_CPU_ALIGNED(u32*, ready_count);
 /* Indicates online CPUs coupled with the current CPU */
 static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled);
 
-/*
- * Used to synchronize entry to deep idle states. Actually per-core rather
- * than per-CPU.
- */
+/* Used to synchronize entry to deep idle states */
 static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier);
 
 /* Saved CPU state across the CPS_PM_POWER_GATED state */
@@ -118,9 +115,10 @@ int cps_pm_enter_state(enum cps_pm_state state)
 	cps_nc_entry_fn entry;
 	struct core_boot_config *core_cfg;
 	struct vpe_boot_config *vpe_cfg;
+	atomic_t *barrier;
 
 	/* Check that there is an entry function for this state */
-	entry = per_cpu(nc_asm_enter, core)[state];
+	entry = per_cpu(nc_asm_enter, cpu)[state];
 	if (!entry)
 		return -EINVAL;
 
@@ -156,7 +154,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
 	smp_mb__after_atomic();
 
 	/* Create a non-coherent mapping of the core ready_count */
-	core_ready_count = per_cpu(ready_count, core);
+	core_ready_count = per_cpu(ready_count, cpu);
 	nc_addr = kmap_noncoherent(virt_to_page(core_ready_count),
 				   (unsigned long)core_ready_count);
 	nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK);
@@ -164,7 +162,8 @@ int cps_pm_enter_state(enum cps_pm_state state)
 
 	/* Ensure ready_count is zero-initialised before the assembly runs */
 	WRITE_ONCE(*nc_core_ready_count, 0);
-	coupled_barrier(&per_cpu(pm_barrier, core), online);
+	barrier = &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu]));
+	coupled_barrier(barrier, online);
 
 	/* Run the generated entry code */
 	left = entry(online, nc_core_ready_count);
@@ -635,12 +634,14 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
 
 static int cps_pm_online_cpu(unsigned int cpu)
 {
-	enum cps_pm_state state;
-	unsigned core = cpu_core(&cpu_data[cpu]);
+	unsigned int sibling, core;
 	void *entry_fn, *core_rc;
+	enum cps_pm_state state;
+
+	core = cpu_core(&cpu_data[cpu]);
 
 	for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
-		if (per_cpu(nc_asm_enter, core)[state])
+		if (per_cpu(nc_asm_enter, cpu)[state])
 			continue;
 		if (!test_bit(state, state_support))
 			continue;
@@ -652,16 +653,19 @@ static int cps_pm_online_cpu(unsigned int cpu)
 			clear_bit(state, state_support);
 		}
 
-		per_cpu(nc_asm_enter, core)[state] = entry_fn;
+		for_each_cpu(sibling, &cpu_sibling_map[cpu])
+			per_cpu(nc_asm_enter, sibling)[state] = entry_fn;
 	}
 
-	if (!per_cpu(ready_count, core)) {
+	if (!per_cpu(ready_count, cpu)) {
 		core_rc = kmalloc(sizeof(u32), GFP_KERNEL);
 		if (!core_rc) {
 			pr_err("Failed allocate core %u ready_count\n", core);
 			return -ENOMEM;
 		}
-		per_cpu(ready_count, core) = core_rc;
+
+		for_each_cpu(sibling, &cpu_sibling_map[cpu])
+			per_cpu(ready_count, sibling) = core_rc;
 	}
 
 	return 0;
-- 
2.17.1


  parent reply	other threads:[~2022-05-25 12:12 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-25 12:10 [PATCH v2 00/12] MIPS: Support I6500 multi-cluster configuration Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 01/12] MIPS: CPS: Add a couple of multi-cluster utility functions Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 02/12] MIPS: GIC: Generate redirect block accessors Dragan Mladjenovic
2022-05-25 18:33   ` Jiaxun Yang
2022-05-25 12:10 ` [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:05   ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 04/12] irqchip: mips-gic: Support multi-cluster in gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:13   ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 05/12] irqchip: mips-gic: Setup defaults in each cluster Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support Dragan Mladjenovic
2022-06-06 11:47   ` Marc Zyngier
2022-06-07 18:23     ` Jiaxun Yang
2022-06-08  6:05       ` Marc Zyngier
2022-06-09 10:14         ` Jiaxun Yang
2022-06-09 11:54           ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 07/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Dragan Mladjenovic
2022-06-27 14:17   ` Dragan Mladjenovic
2022-06-27 14:27     ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 08/12] clocksource: mips-gic-timer: Enable counter when CPUs start Dragan Mladjenovic
2022-05-25 12:10 ` Dragan Mladjenovic [this message]
2022-05-25 12:10 ` [PATCH v2 10/12] MIPS: CPS: Introduce struct cluster_boot_config Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 11/12] MIPS: Report cluster in /proc/cpuinfo Dragan Mladjenovic
2022-06-06 13:14   ` Marc Zyngier
2022-06-07 18:27     ` Jiaxun Yang
2022-06-08  6:13       ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 12/12] MIPS: CPS: Boot CPUs in secondary clusters Dragan Mladjenovic

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