All of lore.kernel.org
 help / color / mirror / Atom feed
From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	<wim@linux-watchdog.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	"Nathan Chancellor" <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>,
	<singo.chang@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v22 09/24] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Thu, 26 May 2022 19:02:18 +0800	[thread overview]
Message-ID: <20220526110233.20080-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20220526110233.20080-1-nancy.lin@mediatek.com>

Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.

1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++++------------
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 999be064103b..ec4f2d90c05a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
 #include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
@@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
@@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
@@ -288,13 +293,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
+
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
 	if (assert)
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      0, NULL);
 	else
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      BIT(id), NULL);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -351,18 +362,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	spin_lock_init(&mmsys->lock);
-
-	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
-	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
-	mmsys->rcdev.of_node = pdev->dev.of_node;
-	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
-	if (ret) {
-		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
-		return ret;
-	}
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "Couldn't get mmsys resource\n");
@@ -384,6 +383,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		mmsys->data = match_data->drv_data[0];
 	}
 
+	spin_lock_init(&mmsys->lock);
+
+	mmsys->rcdev.owner = THIS_MODULE;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+	mmsys->rcdev.of_node = pdev->dev.of_node;
+	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+		return ret;
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..20a271b80b3b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u32 num_resets;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	<wim@linux-watchdog.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: devicetree@vger.kernel.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	David Airlie <airlied@linux.ie>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	singo.chang@mediatek.com, llvm@lists.linux.dev,
	Nick Desaulniers <ndesaulniers@google.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Nathan Chancellor <nathan@kernel.org>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v22 09/24] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Thu, 26 May 2022 19:02:18 +0800	[thread overview]
Message-ID: <20220526110233.20080-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20220526110233.20080-1-nancy.lin@mediatek.com>

Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.

1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++++------------
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 999be064103b..ec4f2d90c05a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
 #include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
@@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
@@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
@@ -288,13 +293,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
+
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
 	if (assert)
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      0, NULL);
 	else
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      BIT(id), NULL);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -351,18 +362,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	spin_lock_init(&mmsys->lock);
-
-	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
-	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
-	mmsys->rcdev.of_node = pdev->dev.of_node;
-	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
-	if (ret) {
-		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
-		return ret;
-	}
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "Couldn't get mmsys resource\n");
@@ -384,6 +383,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		mmsys->data = match_data->drv_data[0];
 	}
 
+	spin_lock_init(&mmsys->lock);
+
+	mmsys->rcdev.owner = THIS_MODULE;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+	mmsys->rcdev.of_node = pdev->dev.of_node;
+	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+		return ret;
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..20a271b80b3b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u32 num_resets;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	<wim@linux-watchdog.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	"Nathan Chancellor" <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>,
	<singo.chang@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v22 09/24] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Thu, 26 May 2022 19:02:18 +0800	[thread overview]
Message-ID: <20220526110233.20080-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20220526110233.20080-1-nancy.lin@mediatek.com>

Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.

1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++++------------
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 999be064103b..ec4f2d90c05a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
 #include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
@@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
@@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
@@ -288,13 +293,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
+
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
 	if (assert)
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      0, NULL);
 	else
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      BIT(id), NULL);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -351,18 +362,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	spin_lock_init(&mmsys->lock);
-
-	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
-	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
-	mmsys->rcdev.of_node = pdev->dev.of_node;
-	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
-	if (ret) {
-		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
-		return ret;
-	}
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "Couldn't get mmsys resource\n");
@@ -384,6 +383,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		mmsys->data = match_data->drv_data[0];
 	}
 
+	spin_lock_init(&mmsys->lock);
+
+	mmsys->rcdev.owner = THIS_MODULE;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+	mmsys->rcdev.of_node = pdev->dev.of_node;
+	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+		return ret;
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..20a271b80b3b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u32 num_resets;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	<wim@linux-watchdog.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	"Nathan Chancellor" <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>,
	<singo.chang@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v22 09/24] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Thu, 26 May 2022 19:02:18 +0800	[thread overview]
Message-ID: <20220526110233.20080-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20220526110233.20080-1-nancy.lin@mediatek.com>

Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.

1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->data" code section for getting the num_resets in mmsys->data.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++++------------
 drivers/soc/mediatek/mtk-mmsys.h |  1 +
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 999be064103b..ec4f2d90c05a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -20,6 +20,8 @@
 #include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
+#define MMSYS_SW_RESET_PER_REG 32
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
 	.routes = mmsys_default_routing_table,
@@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
@@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
@@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
+	.num_resets = 32,
 };
 
 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
@@ -288,13 +293,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 {
 	struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
 	unsigned long flags;
+	u32 offset;
+
+	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+	id = id % MMSYS_SW_RESET_PER_REG;
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
 	if (assert)
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      0, NULL);
 	else
-		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
+		mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + offset, BIT(id),
+				      BIT(id), NULL);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
@@ -351,18 +362,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	spin_lock_init(&mmsys->lock);
-
-	mmsys->rcdev.owner = THIS_MODULE;
-	mmsys->rcdev.nr_resets = 32;
-	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
-	mmsys->rcdev.of_node = pdev->dev.of_node;
-	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
-	if (ret) {
-		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
-		return ret;
-	}
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "Couldn't get mmsys resource\n");
@@ -384,6 +383,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		mmsys->data = match_data->drv_data[0];
 	}
 
+	spin_lock_init(&mmsys->lock);
+
+	mmsys->rcdev.owner = THIS_MODULE;
+	mmsys->rcdev.nr_resets = mmsys->data->num_resets;
+	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
+	mmsys->rcdev.of_node = pdev->dev.of_node;
+	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
+		return ret;
+	}
+
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
 	if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..20a271b80b3b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u32 num_resets;
 };
 
 struct mtk_mmsys_match_data {
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-05-26 11:02 UTC|newest]

Thread overview: 188+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-26 11:02 [PATCH v22 00/24] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2022-05-26 11:02 ` Nancy.Lin
2022-05-26 11:02 ` Nancy.Lin
2022-05-26 11:02 ` Nancy.Lin
2022-05-26 11:02 ` [PATCH v22 01/24] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02 ` [PATCH v22 02/24] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02 ` [PATCH v22 03/24] dt-bindings: mediatek: add ethdr definition for mt8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02 ` [PATCH v22 04/24] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:07   ` Rex-BC Chen
2022-06-09  2:07     ` Rex-BC Chen
2022-06-09  2:07     ` Rex-BC Chen
2022-06-09  2:07     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 05/24] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:08   ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 06/24] soc: mediatek: add mtk_mmsys_update_bits API Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:08   ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-06-09  2:08     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 07/24] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:09   ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 08/24] soc: mediatek: add cmdq support of " Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:09   ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-05-26 11:02 ` Nancy.Lin [this message]
2022-05-26 11:02   ` [PATCH v22 09/24] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:09   ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-06-09  2:09     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 10/24] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:10   ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 11/24] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:10   ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 12/24] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:10   ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-06-09  2:10     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 13/24] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:11   ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 14/24] drm/mediatek: add display merge advance config API " Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:11   ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 15/24] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:11   ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-06-09  2:11     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 16/24] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:12   ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 17/24] drm/mediatek: add display merge async reset control Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:12   ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-06-09  2:12     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 18/24] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:13   ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 19/24] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:13   ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-06-09  2:13     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 20/24] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:14   ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 21/24] drm/mediatek: add dma dev get function Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:14   ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 22/24] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:14   ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-06-09  2:14     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 23/24] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:15   ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-05-26 11:02 ` [PATCH v22 24/24] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-05-26 11:02   ` Nancy.Lin
2022-06-09  2:15   ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-06-09  2:15     ` Rex-BC Chen
2022-06-06  8:42 ` [PATCH v22 00/24] Add MediaTek SoC DRM (vdosys1) support for mt8195 Rex-BC Chen
2022-06-06  8:42   ` Rex-BC Chen
2022-06-06  8:42   ` Rex-BC Chen
2022-06-06  8:42   ` Rex-BC Chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220526110233.20080-10-nancy.lin@mediatek.com \
    --to=nancy.lin@mediatek.com \
    --cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
    --cc=airlied@linux.ie \
    --cc=angelogioacchino.delregno@collabora.com \
    --cc=chunkuang.hu@kernel.org \
    --cc=daniel@ffwll.ch \
    --cc=devicetree@vger.kernel.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=jason-jh.lin@mediatek.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=linux@roeck-us.net \
    --cc=llvm@lists.linux.dev \
    --cc=matthias.bgg@gmail.com \
    --cc=nathan@kernel.org \
    --cc=ndesaulniers@google.com \
    --cc=p.zabel@pengutronix.de \
    --cc=robh+dt@kernel.org \
    --cc=singo.chang@mediatek.com \
    --cc=wim@linux-watchdog.org \
    --cc=yongqiang.niu@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.