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From: Conor Dooley <conor.dooley@microchip.com>
To: Wolfgang Grandegger <wg@grandegger.com>,
	Marc Kleine-Budde <mkl@pengutronix.de>,
	"David S . Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	<linux-can@vger.kernel.org>, <netdev@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>
Subject: [PATCH net-next 2/2] riscv: dts: microchip: add mpfs's can controllers
Date: Tue, 7 Jun 2022 07:55:00 +0100	[thread overview]
Message-ID: <20220607065459.2035746-3-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220607065459.2035746-1-conor.dooley@microchip.com>

PolarFire SoC has a pair of can controllers, but as they were
undocumented there were omitted from the device tree. Add them.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/microchip-mpfs.dtsi     | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index cf2f55e1dcb6..059a671314bf 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -326,6 +326,24 @@ i2c1: i2c@2010b000 {
 			status = "disabled";
 		};
 
+		can0: can@2010c000 {
+			compatible = "microchip,mpfs-can";
+			reg = <0x0 0x2010c000 0x0 0x1000>;
+			clocks = <&clkcfg CLK_CAN0>;
+			interrupt-parent = <&plic>;
+			interrupts = <56>;
+			status = "disabled";
+		};
+
+		can1: can@2010d000 {
+			compatible = "microchip,mpfs-can";
+			reg = <0x0 0x2010d000 0x0 0x1000>;
+			clocks = <&clkcfg CLK_CAN1>;
+			interrupt-parent = <&plic>;
+			interrupts = <57>;
+			status = "disabled";
+		};
+
 		mac0: ethernet@20110000 {
 			compatible = "cdns,macb";
 			reg = <0x0 0x20110000 0x0 0x2000>;
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Wolfgang Grandegger <wg@grandegger.com>,
	Marc Kleine-Budde <mkl@pengutronix.de>,
	"David S . Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	<linux-can@vger.kernel.org>, <netdev@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>
Subject: [PATCH net-next 2/2] riscv: dts: microchip: add mpfs's can controllers
Date: Tue, 7 Jun 2022 07:55:00 +0100	[thread overview]
Message-ID: <20220607065459.2035746-3-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220607065459.2035746-1-conor.dooley@microchip.com>

PolarFire SoC has a pair of can controllers, but as they were
undocumented there were omitted from the device tree. Add them.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/microchip-mpfs.dtsi     | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index cf2f55e1dcb6..059a671314bf 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -326,6 +326,24 @@ i2c1: i2c@2010b000 {
 			status = "disabled";
 		};
 
+		can0: can@2010c000 {
+			compatible = "microchip,mpfs-can";
+			reg = <0x0 0x2010c000 0x0 0x1000>;
+			clocks = <&clkcfg CLK_CAN0>;
+			interrupt-parent = <&plic>;
+			interrupts = <56>;
+			status = "disabled";
+		};
+
+		can1: can@2010d000 {
+			compatible = "microchip,mpfs-can";
+			reg = <0x0 0x2010d000 0x0 0x1000>;
+			clocks = <&clkcfg CLK_CAN1>;
+			interrupt-parent = <&plic>;
+			interrupts = <57>;
+			status = "disabled";
+		};
+
 		mac0: ethernet@20110000 {
 			compatible = "cdns,macb";
 			reg = <0x0 0x20110000 0x0 0x2000>;
-- 
2.36.1


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  parent reply	other threads:[~2022-06-07  6:57 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-07  6:54 [PATCH net-next 0/2] Document PolarFire SoC can controller Conor Dooley
2022-06-07  6:54 ` Conor Dooley
2022-06-07  6:54 ` [PATCH net-next 1/2] dt-bindings: can: mpfs: document the mpfs " Conor Dooley
2022-06-07  6:54   ` Conor Dooley
2022-06-07 16:19   ` Rob Herring
2022-06-07 16:19     ` Rob Herring
2022-06-07  6:55 ` Conor Dooley [this message]
2022-06-07  6:55   ` [PATCH net-next 2/2] riscv: dts: microchip: add mpfs's can controllers Conor Dooley
2022-06-07  7:15 ` [PATCH net-next 0/2] Document PolarFire SoC can controller Marc Kleine-Budde
2022-06-07  7:15   ` Marc Kleine-Budde
2022-06-07  7:52   ` Conor.Dooley
2022-06-07  7:52     ` Conor.Dooley
2022-06-07  8:28     ` Marc Kleine-Budde
2022-06-07  8:28       ` Marc Kleine-Budde
2022-06-07  8:54       ` Conor.Dooley
2022-06-07  8:54         ` Conor.Dooley
2022-06-13 12:52         ` Conor.Dooley
2022-06-13 12:52           ` Conor.Dooley
2022-06-13 13:45           ` Marc Kleine-Budde
2022-06-13 13:45             ` Marc Kleine-Budde
2022-06-13 13:48             ` Conor.Dooley
2022-06-13 13:48               ` Conor.Dooley

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