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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH] drm/i915/dg2: Correct DSS check for Wa_1308578152
Date: Tue,  7 Jun 2022 08:47:24 -0700	[thread overview]
Message-ID: <20220607154724.3155521-1-matthew.d.roper@intel.com> (raw)

When converting our DSS masks to bitmaps, we fumbled the condition used
to check whether any DSS are present in the first gslice.  Since
intel_sseu_find_first_xehp_dss() returns a 0-based number, we need a >=
condition rather than >.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Reported-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b191b234160..67104ba8951e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2079,7 +2079,7 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
 {
-	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
 		GEN_DSS_PER_GSLICE;
 }
 
-- 
2.35.3


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dg2: Correct DSS check for Wa_1308578152
Date: Tue,  7 Jun 2022 08:47:24 -0700	[thread overview]
Message-ID: <20220607154724.3155521-1-matthew.d.roper@intel.com> (raw)

When converting our DSS masks to bitmaps, we fumbled the condition used
to check whether any DSS are present in the first gslice.  Since
intel_sseu_find_first_xehp_dss() returns a 0-based number, we need a >=
condition rather than >.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Reported-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b191b234160..67104ba8951e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2079,7 +2079,7 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
 {
-	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
 		GEN_DSS_PER_GSLICE;
 }
 
-- 
2.35.3


             reply	other threads:[~2022-06-07 15:50 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-07 15:47 Matt Roper [this message]
2022-06-07 15:47 ` [Intel-gfx] [PATCH] drm/i915/dg2: Correct DSS check for Wa_1308578152 Matt Roper
2022-06-07 16:07 ` Balasubramani Vivekanandan
2022-06-07 16:07   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-06-07 17:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-06-07 22:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-08  0:54   ` Matt Roper

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